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VHDL-FPGA-Verilog list
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jiafa
Downloaded:0
AD sample the incoming signal sum, comparison, judgment, and output control codes to implement digital AGC
Date
: 2025-09-12
Size
: 1.04mb
User
:
谭振伟
FPGA
Downloaded:0
FPGA UART uartFPGA UART
Date
: 2025-09-12
Size
: 107kb
User
:
杨倩
FPGA_GOOD
Downloaded:0
FPGA interview questions highlights FPGA interview subject highlights
Date
: 2025-09-12
Size
: 209kb
User
:
王勋志
state-machine-diagram
Downloaded:0
Chapter 6, the state machine diagram and its application of Chapter 6 of the state machine diagram and its application
Date
: 2025-09-12
Size
: 434kb
User
:
王勋志
ad7991
Downloaded:0
ad7991 driver suitable for ad79XX series chip driver
Date
: 2025-09-12
Size
: 317kb
User
:
zhangxinpan
div16_dff
Downloaded:0
Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
Date
: 2025-09-12
Size
: 144kb
User
:
longdonghuo
frediv3
Downloaded:0
The project has designed a 3-divider. The circuit structure consists of a D flip-flop and NAND gate, including complete engineering simulation, timing diagram.
Date
: 2025-09-12
Size
: 141kb
User
:
longdonghuo
m_SSRG
Downloaded:0
The engineering design of an m-sequence spread spectrum system, the circuit structure of the SSRG structure has been through the simulation.
Date
: 2025-09-12
Size
: 113kb
User
:
longdonghuo
m_MSRG
Downloaded:0
The engineering design of a spread spectrum system, the use of schematic design method, the circuit structure is MSRG has passed through the simulation, and simulation timing diagram.
Date
: 2025-09-12
Size
: 144kb
User
:
longdonghuo
div16_tff
Downloaded:0
The engineering design of a 16 frequency divider circuit using T flip-flop, through simulation.
Date
: 2025-09-12
Size
: 141kb
User
:
longdonghuo
divide_testbench
Downloaded:0
Description of the division, written very detailed, really good, can be used as an engineering sub-module
Date
: 2025-09-12
Size
: 3kb
User
:
chao
add8
Downloaded:0
8 bits a
Date
: 2025-09-12
Size
: 33kb
User
:
oneway
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