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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 113kb
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  • Author :longd******
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The engineering design of an m-sequence spread spectrum system, the circuit structure of the SSRG structure has been through the simulation.
Packet file list
(Preview for download)
m_SSRG\db\m_ssrg.asm.qmsg
......\..\m_ssrg.cbx.xml
......\..\m_ssrg.cmp.bpm
......\..\m_ssrg.cmp.cdb
......\..\m_ssrg.cmp.ecobp
......\..\m_ssrg.cmp.hdb
......\..\m_ssrg.cmp.logdb
......\..\m_ssrg.cmp.rdb
......\..\m_ssrg.cmp.tdb
......\..\m_ssrg.cmp0.ddb
......\..\m_ssrg.cmp_bb.cdb
......\..\m_ssrg.cmp_bb.hdb
......\..\m_ssrg.cmp_bb.logdb
......\..\m_ssrg.cmp_bb.rcf
......\..\m_ssrg.dbp
......\..\m_ssrg.db_info
......\..\m_ssrg.eco.cdb
......\..\m_ssrg.fit.qmsg
......\..\m_ssrg.hier_info
......\..\m_ssrg.hif
......\..\m_ssrg.map.bpm
......\..\m_ssrg.map.cdb
......\..\m_ssrg.map.ecobp
......\..\m_ssrg.map.hdb
......\..\m_ssrg.map.logdb
......\..\m_ssrg.map.qmsg
......\..\m_ssrg.map_bb.cdb
......\..\m_ssrg.map_bb.hdb
......\..\m_ssrg.map_bb.logdb
......\..\m_ssrg.merge.qmsg
......\..\m_ssrg.pre_map.cdb
......\..\m_ssrg.pre_map.hdb
......\..\m_ssrg.psp
......\..\m_ssrg.pss
......\..\m_ssrg.rtlv.hdb
......\..\m_ssrg.rtlv_sg.cdb
......\..\m_ssrg.rtlv_sg_swap.cdb
......\..\m_ssrg.sgdiff.cdb
......\..\m_ssrg.sgdiff.hdb
......\..\m_ssrg.signalprobe.cdb
......\..\m_ssrg.sld_design_entry.sci
......\..\m_ssrg.sld_design_entry_dsc.sci
......\..\m_ssrg.syn_hier_info
......\..\m_ssrg.tan.qmsg
......\..\wed.wsf
......\m_ssrg.asm.rpt
......\m_ssrg.bdf
......\m_ssrg.done
......\m_ssrg.fit.rpt
......\m_ssrg.fit.smsg
......\m_ssrg.fit.summary
......\m_ssrg.flow.rpt
......\m_ssrg.map.rpt
......\m_ssrg.map.summary
......\m_ssrg.merge.rpt
......\m_ssrg.pin
......\m_ssrg.pof
......\m_ssrg.qpf
......\m_ssrg.qsf
......\m_ssrg.qws
......\m_ssrg.sof
......\m_ssrg.tan.rpt
......\m_ssrg.vwf
......\db
m_SSRG
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