VHDL-FPGA-Verilog List Page 1509

VHDL-FPGA-Verilog list

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counter-interrupt-8-timer-04s Downloaded：0: SCM source (keilC language)--- counter interrupt 8 timer 04s
Date : 2025-09-12 Size : 8kb User : 除魔为道
ADS7822-data-collection Downloaded：1: the ads7822 data acquisition, the Verilog language, collected results into the IEEE754 single precision floating-point output
Date : 2025-09-12 Size : 105kb User : seven
pci_to_wb_latest[1].tar Downloaded：0: This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I m really trying to st
Date : 2025-09-12 Size : 7kb User : hxr
a_vhdl_8253_timer_latest[1].tar Downloaded：0: a VHDL version of the Intel 8254 timer
Date : 2025-09-12 Size : 105kb User : hxr
wb_to_amba_latest[1].tar Downloaded：0: A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
Date : 2025-09-12 Size : 11kb User : hxr
The-design-of-the-bicycle-odometer Downloaded：0: The design of the bicycle odometer
Date : 2025-09-12 Size : 206kb User : 除魔为道
Foreign-language-translation Downloaded：0: The design of the bicycle odometer
Date : 2025-09-12 Size : 13kb User : 除魔为道
Temperature-Meter Downloaded：0: Temperature Meter in VHDL code.
Date : 2025-09-12 Size : 1kb User : Andre Michels
compare Downloaded：0: IsPLSI1016E_80LJ44 chip sixteen
Date : 2025-09-12 Size : 3kb User : 马爱华
Chronometer Downloaded：0: Chronometer VHDL code.
Date : 2025-09-12 Size : 2kb User : Andre Michels
timer Downloaded：0: Clock with verilog and debug on the DE2 board
Date : 2025-09-12 Size : 781kb User : fisher
Fibonacci-Sequence Downloaded：0: Fibonacci Sequence VHDL code.
Date : 2025-09-12 Size : 1kb User : Andre Michels

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