VHDL-FPGA-Verilog List Page 1510

VHDL-FPGA-Verilog list

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DIGITAL-CLOCK(WORKING-PROPERLY) Downloaded：0: it is the clock based on 8051
Date : 2025-09-12 Size : 6kb User : pari
traffic-lights Downloaded：0: A simple control system for traffic lights, no fault processing function
Date : 2025-09-12 Size : 24kb User : 娅宣
Sinusoidal-Filter Downloaded：0: This a simple sine wave filtering procedures
Date : 2025-09-12 Size : 263kb User : 娅宣
LCD1 Downloaded：0: lcd code for microcontroller
Date : 2025-09-12 Size : 1kb User : pari
FIFO Downloaded：0: Verilog HDL language, asynchronous FIFO
Date : 2025-09-12 Size : 3kb User : 赵鑫
VHDL Downloaded：0: Control Link Serial Interface with Manchester and CDR
Date : 2025-09-12 Size : 13kb User : chengjw
ddr2_sdram_latest[1].tar Downloaded：0: DDR2 the sdram controller VHDL source code
Date : 2025-09-12 Size : 1.7mb User : hxr
FPGA--DDS Downloaded：0: This paper introduced the method of using FPGA to instead DDS that have the same function.
Date : 2025-09-12 Size : 269kb User : 陈楠
msp430x41x Downloaded：0: Low Supply-Voltage Range, 1.8 V to 3.6 V Ultralow-Power Consumption: − Active Mode: 280 µ A at 1 MHz, 2.2 V − Standby Mode: 1.1 µ A − Off Mode (RAM Retention): 0.1 µ A Five Power Saving Mode
Date : 2025-09-12 Size : 1.84mb User : 苏春明
A7105-Datasheet-v1.1 Downloaded：0: 0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify description of state machine and FIFO mode Rename IRQS1/I
Date : 2025-09-12 Size : 1.88mb User : 苏春明
ddr_sdr_latest[1].tar Downloaded：0: The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
Date : 2025-09-12 Size : 79kb User : hxr
Hall-element-tachometer-circuit Downloaded：0: Hall element tachometer circuit
Date : 2025-09-12 Size : 60kb User : 除魔为道

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