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VHDL-FPGA-Verilog list
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dds
Downloaded:0
The application XLINIX the DDS implementation and simulation, students preliminary VHDL design is a useful help
Date
: 2025-11-19
Size
: 735kb
User
:
王鹏
ENTITY-seg70-IS
Downloaded:0
Choice function VHDL to digital display value, we must first generate the bit-select signal, that is, select a digital tube to display the value Secondly, to give a given segment select signal, the digital tube display w
Date
: 2025-11-19
Size
: 3kb
User
:
袁浩然
12864VHDL
Downloaded:0
12864 display
Date
: 2025-11-19
Size
: 239kb
User
:
tao
MCUinterrupt
Downloaded:0
51 MCU interrupt the program, to light the LED lights, the S & P in the SCM
Date
: 2025-11-19
Size
: 288kb
User
:
李浩
hlab3_solution
Downloaded:0
console for uart verilog verilog verilog verilog
Date
: 2025-11-19
Size
: 279kb
User
:
kwoksama
A-variety-of-dividers-program
Downloaded:0
A variety of dividers program
Date
: 2025-11-19
Size
: 6kb
User
:
胡伟红
Counter-and-digital-tube-display
Downloaded:0
This article ten, 12, 16, and six decimal counter counting process, six decimal counter, the status of digital tube display, and data scanning time-sharing module and decoder modules in the five digital tube . After the
Date
: 2025-11-19
Size
: 255kb
User
:
胡伟红
Verilog
Downloaded:0
Very useful tutorial, easy to understand for novice users.
Date
: 2025-11-19
Size
: 1.25mb
User
:
q
Traffic-lights-program
Downloaded:0
The design of a traffic signal control circuits. Requirements: 1, main roads and branch roads alternately release, the main road each release of 30 seconds, the branch roads each release of 20 seconds. 2, each time the g
Date
: 2025-11-19
Size
: 19kb
User
:
胡伟红
UART
Downloaded:0
A high-speed serial port using a lookup table to write the provincial resources
Date
: 2025-11-19
Size
: 386kb
User
:
wangshaoyang
LPF_10K
Downloaded:0
10KHz bandwidth 1Bit digtal fir filter at 10MSps
Date
: 2025-11-19
Size
: 2kb
User
:
duzhk
week_9
Downloaded:0
VHDL program counter is a one-source code
Date
: 2025-11-19
Size
: 198kb
User
:
wuzw
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