VHDL-FPGA-Verilog List Page 1234

VHDL-FPGA-Verilog list

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da.fir Downloaded：0: The ADC filter design, a reference to those beginner ADC students, veterans do not laugh at me
Date : 2026-01-19 Size : 37kb User : zhaorongjian
edg_test_design Downloaded：0: Edge detection circuit program is very important for language learning FPGA using Verilog language.
Date : 2026-01-19 Size : 301kb User : zhaorongjian
exp2 Downloaded：0: Light water experiments, are forward reverse function, water lamp light off sequentially. .
Date : 2026-01-19 Size : 52kb User : zhaorongjian
Quartus91Crack Downloaded：0: Quartus91Crack, crack Xiangjie
Date : 2026-01-19 Size : 1.73mb User : 赵岩
Virtex-5-FPGA-Data-Sheet Downloaded：0: The program xilinx fpga, v5, verilog language, mainly used for data acquisition, acquisition frequency of up to 500m, through data forwarding pingpang cache.
Date : 2026-01-19 Size : 682kb User : fuhai
Virtex-5-Family-Overview Downloaded：0: This article is xilinx fpga v5 overall introduction of the chip family, famliy view
Date : 2026-01-19 Size : 148kb User : fuhai
Virtex-5-FPGA-User-Guide Downloaded：0: This article based on the the xilinx fpga v5 chip introduces how to use, user guide
Date : 2026-01-19 Size : 4.62mb User : fuhai
RocketIO-GTX-Transceiver-User-Guide Downloaded：0: This article is based the xilinx fpga v5, introduced the use of the rocket io
Date : 2026-01-19 Size : 4.28mb User : fuhai
Virtex-5-FPGA-PCB-Designers-Guide Downloaded：0: This article is based the xilinx fpga v5, introduces some of the issues when making PCB
Date : 2026-01-19 Size : 620kb User : fuhai
Ethernet-MAC-User-Guide Downloaded：0: Based xilinx fpga, v5, describes how to use the FPGA making Ethernet
Date : 2026-01-19 Size : 2.28mb User : fuhai
bin2chuan Downloaded：0: // This an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_count(input clock , output reg [31:0] counter_out) always @ (posedge clock)//
Date : 2026-01-19 Size : 312kb User : zhanghf
chuan2bing Downloaded：0: module b_c(dout,clk,clr,din) output dout input [3:0] din input clk,clr reg dout reg [3:0] q reg [1:0] cnt always@(posedge clk) begin cnt<=cnt+1 if(clr) q<=0 else begin if(cnt>0) q[3:1]<=q[2:0] else if(cnt==0) q<=din end
Date : 2026-01-19 Size : 1.61mb User : zhanghf

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