VHDL-FPGA-Verilog List Page 1230

VHDL-FPGA-Verilog list

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ymq_38 Downloaded：0: This code use verilog language realization and decoder, in led to display the results.
Date : 2025-08-25 Size : 2.17mb User : 边茂宣
code Downloaded：0: 32bits full adder
Date : 2025-08-25 Size : 1kb User : 许阳
code Downloaded：0: The 32bits pipelined adder verilog language, xilinx chip run through
Date : 2025-08-25 Size : 1kb User : 许阳
daima Downloaded：0: The 32bits carry select adder verilog language, xilinx chip run through
Date : 2025-08-25 Size : 1kb User : 许阳
daima Downloaded：0: The 32bits advance carry adder verilog language, xilinx chip run through
Date : 2025-08-25 Size : 43kb User : 许阳
code Downloaded：0: The 32bits complement adder verilog language, xilinx chip run through
Date : 2025-08-25 Size : 1kb User : 许阳
Matrix_Keyboard Downloaded：0: Verilog prepared 4x4 matrix keyboard scan code and it s directly available in QurtursII . The concrete realization of the function: key is pressed, the digital tube to the corresponding display 0,1 ... E, F
Date : 2025-08-25 Size : 253kb User : wicoboy
Pll_prj Downloaded：0: The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control two LED lights flicker, flicker frequency can be used to
Date : 2025-08-25 Size : 142kb User : wicoboy
sick_room_call Downloaded：0: Digital Circuit Design Title: FPGA implementation of the ward call system. The subject of the request: support call memory function, call priority, nurse duty room can give the ward call response signal.
Date : 2025-08-25 Size : 485kb User : wicoboy
SinPout Downloaded：0: It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
Date : 2025-08-25 Size : 232kb User : wicoboy
Snatch Downloaded：0: Digital Circuit Design Title: Responder. Function: Moderator press after the start of Responder, or foul once someone answer in other players Responder shall be shielded score subtraction and digital tube display to answ
Date : 2025-08-25 Size : 1.09mb User : wicoboy
Traffic_Light Downloaded：0: The FPGA simulation realization of traffic light control system, language, Verilog, environment QurtursII, default preset time countdown, support manual control mode for a direction signal lamps lit. Signal lights using
Date : 2025-08-25 Size : 610kb User : wicoboy

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