VHDL-FPGA-Verilog List Page 1227

VHDL-FPGA-Verilog list

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sdram_mdl Downloaded：0: Sdram of privileged students to read and write code, suitable for beginners to learn, very detailed notes.
Date : 2025-08-25 Size : 2.09mb User : luyixiao
DE2_70_LTM_Ephoto Downloaded：0: Picture display size of 800 x 480 and can touch a browse before or after the picture on the LTM
Date : 2025-08-25 Size : 5.15mb User : 钟治薇
DE2_115_CAMERA Downloaded：0: DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA
Date : 2025-08-25 Size : 275kb User : 钟治薇
lab5_files Downloaded：0: Applications and source code analysis of the FPGA ROM and RAM
Date : 2025-08-25 Size : 463kb User : 黄端阳
lab7_files Downloaded：0: Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code
Date : 2025-08-25 Size : 2.01mb User : 黄端阳
lab7_supplemental_files Downloaded：0: Based on the interpretation and application of FPGA PS2 as well as the example of a large number of source
Date : 2025-08-25 Size : 275kb User : 黄端阳
lab3_files Downloaded：0: FPGA counter-based analysis and source code, and how to write testbench
Date : 2025-08-25 Size : 765kb User : 黄端阳
bitsynchro Downloaded：0: The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.
Date : 2025-08-25 Size : 1kb User : 任
divider Downloaded：0: The Verilog language divider for digital contest Responder design module one
Date : 2025-08-25 Size : 1kb User : zhuojun chen
decoder Downloaded：0: Verilog prepared encoder, as well as excitation input code
Date : 2025-08-25 Size : 1kb User : zhuojun chen
38-decoder Downloaded：0: The 3-8 decoder Verilog hardware language development environment is ModelSim
Date : 2025-08-25 Size : 3kb User : klxl
4-to-1-digital-selector Downloaded：0: 4 to 1 digital selector Verilog hardware language development environment ModelSim
Date : 2025-08-25 Size : 3kb User : klxl

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