VHDL-FPGA-Verilog List Page 1224

VHDL-FPGA-Verilog list

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quadratic_func_latest.tar Downloaded：0: quadratic function for vhdl language
Date : 2025-08-25 Size : 350kb User : sasa
serial_div_uu_latest.tar Downloaded：0: serial divide with testbench
Date : 2025-08-25 Size : 11kb User : sasa
my_fir Downloaded：0: Verilog write FIR filter, modelsim simulation through
Date : 2025-08-25 Size : 1kb User : 韩帅
projet Downloaded：0: Nous nous proposons de construire un système d’acquisition à partir du « SPARTAN 3A FPGA starter kit board » de XILINX et des périphériques de cette carte dans le cadre du TP « acquisition de données » .
Date : 2025-08-25 Size : 361kb User : ELRIFAI
xilinx-primitive.zip Downloaded：0: xilinx primitives use manual xilinx company to provide users with library functions.
Date : 2025-08-25 Size : 2.55mb User : wang qian
CLB.zip Downloaded：0: CLB configurable logic block documentation describes the structure and use of the CLB.
Date : 2025-08-25 Size : 737kb User : wang qian
Xilinx_DCM.zip Downloaded：0: xilinx DCM function documentation describes the structure and use of DCM.
Date : 2025-08-25 Size : 8kb User : wang qian
AMBA_AHB.rar Downloaded：0: amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
Date : 2025-08-25 Size : 5kb User : videv
VGA_controller.rar Downloaded：0: VGA controller, the controller according to the timing requirements of the video DA, to provide control signals and RGB video data.
Date : 2025-08-25 Size : 1kb User : 谢敏
pwm.rar Downloaded：0: To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes
Date : 2025-08-25 Size : 161kb User : 廊桥拾梦
Memory_BIST.rar Downloaded：0: Memory_BIST a memory controller and used in memory sequence indentification
Date : 2025-08-25 Size : 114kb User : videv
DE2_Default.zip Downloaded：0: DE2 development board DEMO source project, a good reference value, also can use it to re-download to the board.
Date : 2025-08-25 Size : 5.06mb User : 韩帅

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