VHDL-FPGA-Verilog List Page 1226

VHDL-FPGA-Verilog list

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The-D-flip-flop Downloaded：0: The D flip-flop of the Verilog hardware language development environment is ModelSim
Date : 2025-08-25 Size : 3kb User : klxl
FPGAdigital-tube Downloaded：0: Single button control four digital tube, press down, hold down the digital display figures from small to large increments, release the button, digital implementation decreasing.
Date : 2025-08-25 Size : 385kb User : 蒋兰
SDcard Downloaded：0: A SD card reader program can use SPI mode (VHDL)
Date : 2025-08-25 Size : 2kb User : 罗亚
uart_tx_rx_baudselct Downloaded：0: A uart source code using Verilog language design, baud rate selection.
Date : 2025-08-25 Size : 3kb User : Andy Zhou
Dm9000a_Init Downloaded：0: The DM9000 network port communications chip control module, FPGA-based control module initialization, sending and receiving data
Date : 2025-08-25 Size : 24.21mb User : 姜新洲
vga_pic_70 Downloaded：0: VGA control program, a raster image of the selective output, mainly the control of the VGA
Date : 2025-08-25 Size : 4.58mb User : 姜新洲
sdram_48LC16M16A Downloaded：0: 48LC16M16A SDRAM chip FPGA controller program
Date : 2025-08-25 Size : 2.85mb User : 姜新洲
QPSK_R Downloaded：0: FPGA implementation of QPSK QPSK modulation to achieve
Date : 2025-08-25 Size : 13.3mb User : 姜新洲
QPSK_T Downloaded：0: FPGA implementation of QPSK demodulator，VERILOG source
Date : 2025-08-25 Size : 3.88mb User : 姜新洲
AD976_6channel Downloaded：0: The software is based on vhdl for FPGA,which is used for electronic transformer fulfil IEC6185-9 protocol.the AD chip is AD976,it works at the state of 6 channels at the same time.
Date : 2025-08-25 Size : 15kb User : cjp
mu_12channel Downloaded：0: The software is developed for merging unit under IEC61850-9-1 protocol,12 channels.
Date : 2025-08-25 Size : 324kb User : cjp
Xilinx_Workshop-Design_Primer Downloaded：0: Xilinx Workshop FPGA Digital System Design Primer one
Date : 2025-08-25 Size : 5.51mb User : zhibo_zhu

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