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VHDL-FPGA-Verilog list
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multiplex
Downloaded:0
Quad information time-division multiplexing and demultiplexing, contains the string conversion, parallel-serial conversion, extracting the frame synchronization, frequency division, the shift register.
Date
: 2025-08-25
Size
: 1.13mb
User
:
yingao
KEY_LED
Downloaded:0
light led
Date
: 2025-08-25
Size
: 1kb
User
:
李木
fenpin
Downloaded:0
1-62553 any divide the file containing the test file, is a good choice.
Date
: 2025-08-25
Size
: 1kb
User
:
张学仁
EDA
Downloaded:0
EDA training. Divider circuit design. Finite state machine. Modelsim simulation FPGA chip resource utilization
Date
: 2025-08-25
Size
: 1.4mb
User
:
wangfan
no1
Downloaded:0
VHDL to do 16-bit parallel input to 16 synchronous serial output
Date
: 2025-08-25
Size
: 3kb
User
:
vga_controller_xilinx
Downloaded:0
Xilinx under VGA interface program and project files
Date
: 2025-08-25
Size
: 1.01mb
User
:
annlair
V
Downloaded:0
FPGA implementation of a table tennis game
Date
: 2025-08-25
Size
: 7kb
User
:
annlair
TEST
Downloaded:0
Xilinx///Microblaze to add manually LCDIP test program
Date
: 2025-08-25
Size
: 2kb
User
:
annlair
MCP3301ADC
Downloaded:0
VerilogHDL write the analog-to-digital conversion chip MCP3301 timing, its ModelSim simulation file
Date
: 2025-08-25
Size
: 111kb
User
:
彭治国
DI
Downloaded:0
This is a the duty cycle VerilogHDL calculated program to input a signal to be measured, and then outputs Ton, Toff. Unit is us
Date
: 2025-08-25
Size
: 11kb
User
:
彭治国
RAM
Downloaded:0
the RAM the source single port structure altera FPGA
Date
: 2025-08-25
Size
: 714kb
User
:
lenovo
PWM
Downloaded:0
CPLD-based multi-channel PWM to achieve single-chip serial transmission duty cycle data
Date
: 2025-08-25
Size
: 203kb
User
:
李永
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