// This an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_count(input clock , output reg [31:0] counter_out) always @ (posedge clock)// on positive clock edge begin counter_out <=#1 counter_out+ 1 // increment counter end endmodule// end of module counter

并串转换\b_c.asm.rpt
........\b_c.done
........\b_c.eda.rpt
........\b_c.fit.rpt
........\b_c.fit.smsg
........\b_c.fit.summary
........\b_c.flow.rpt
........\b_c.map.rpt
........\b_c.map.summary
........\b_c.pin
........\b_c.pof
........\b_c.qpf
........\b_c.qsf
........\b_c.qws
........\b_c.sim.rpt
........\b_c.sof
........\b_c.tan.rpt
........\b_c.tan.summary
........\b_c.v
........\b_c.v.bak
........\b_c.vwf
........\db\b_c.asm.qmsg
........\..\b_c.asm_labs.ddb
........\..\b_c.cbx.xml
........\..\b_c.cmp.bpm
........\..\b_c.cmp.cdb
........\..\b_c.cmp.ecobp
........\..\b_c.cmp.hdb
........\..\b_c.cmp.kpt
........\..\b_c.cmp.logdb
........\..\b_c.cmp.rdb
........\..\b_c.cmp.tdb
........\..\b_c.cmp0.ddb
........\..\b_c.cmp_merge.kpt
........\..\b_c.db_info
........\..\b_c.eco.cdb
........\..\b_c.eda.qmsg
........\..\b_c.eds_overflow
........\..\b_c.fit.qmsg
........\..\b_c.fnsim.cdb
........\..\b_c.fnsim.hdb
........\..\b_c.fnsim.qmsg
........\..\b_c.hier_info
........\..\b_c.hif
........\..\b_c.lpc.html
........\..\b_c.lpc.rdb
........\..\b_c.lpc.txt
........\..\b_c.map.bpm
........\..\b_c.map.cdb
........\..\b_c.map.ecobp
........\..\b_c.map.hdb
........\..\b_c.map.kpt
........\..\b_c.map.logdb
........\..\b_c.map.qmsg
........\..\b_c.map_bb.cdb
........\..\b_c.map_bb.hdb
........\..\b_c.map_bb.logdb
........\..\b_c.pre_map.cdb
........\..\b_c.pre_map.hdb
........\..\b_c.rtlv.hdb
........\..\b_c.rtlv_sg.cdb
........\..\b_c.rtlv_sg_swap.cdb
........\..\b_c.sgdiff.cdb
........\..\b_c.sgdiff.hdb
........\..\b_c.sim.cvwf
........\..\b_c.sim.hdb
........\..\b_c.sim.qmsg
........\..\b_c.sim.rdb
........\..\b_c.simfam
........\..\b_c.sld_design_entry.sci
........\..\b_c.sld_design_entry_dsc.sci
........\..\b_c.syn_hier_info
........\..\b_c.tan.qmsg
........\..\b_c.tis_db_list.ddb
........\..\b_c.tmw_info
........\..\b_c_global_asgn_op.abo
........\..\prev_cmp_b_c.asm.qmsg
........\..\prev_cmp_b_c.eda.qmsg
........\..\prev_cmp_b_c.fit.qmsg
........\..\prev_cmp_b_c.map.qmsg
........\..\prev_cmp_b_c.qmsg
........\..\prev_cmp_b_c.sim.qmsg
........\..\prev_cmp_b_c.tan.qmsg
........\..\wed.wsf
........\incremental_db\compiled_partitions\b_c.root_partition.cmp.atm
........\..............\...................\b_c.root_partition.cmp.cfm
........\..............\...................\b_c.root_partition.cmp.dfp
........\..............\...................\b_c.root_partition.cmp.hdbx
........\..............\...................\b_c.root_partition.cmp.kpt
........\..............\...................\b_c.root_partition.cmp.logdb
........\..............\...................\b_c.root_partition.cmp.rcf
........\..............\...................\b_c.root_partition.map.atm
........\..............\...................\b_c.root_partition.map.dpi
........\..............\...................\b_c.root_partition.map.hdbx
........\..............\...................\b_c.root_partition.map.kpt
........\..............\README
........\..............\compiled_partitions
........\db
........\incremental_db
并串转换

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