Edge detection circuit program is very important for language learning FPGA using Verilog language.

edg_test_design
...............\db
...............\..\edg_test_design.asm.qmsg
...............\..\edg_test_design.asm_labs.ddb
...............\..\edg_test_design.cbx.xml
...............\..\edg_test_design.cmp.bpm
...............\..\edg_test_design.cmp.cdb
...............\..\edg_test_design.cmp.ecobp
...............\..\edg_test_design.cmp.hdb
...............\..\edg_test_design.cmp.logdb
...............\..\edg_test_design.cmp.rdb
...............\..\edg_test_design.cmp.tdb
...............\..\edg_test_design.cmp0.ddb
...............\..\edg_test_design.cmp_bb.cdb
...............\..\edg_test_design.cmp_bb.hdb
...............\..\edg_test_design.cmp_bb.logdb
...............\..\edg_test_design.cmp_bb.rcf
...............\..\edg_test_design.dbp
...............\..\edg_test_design.db_info
...............\..\edg_test_design.eco.cdb
...............\..\edg_test_design.fit.qmsg
...............\..\edg_test_design.hier_info
...............\..\edg_test_design.hif
...............\..\edg_test_design.map.bpm
...............\..\edg_test_design.map.cdb
...............\..\edg_test_design.map.ecobp
...............\..\edg_test_design.map.hdb
...............\..\edg_test_design.map.logdb
...............\..\edg_test_design.map.qmsg
...............\..\edg_test_design.map_bb.cdb
...............\..\edg_test_design.map_bb.hdb
...............\..\edg_test_design.map_bb.logdb
...............\..\edg_test_design.pre_map.cdb
...............\..\edg_test_design.pre_map.hdb
...............\..\edg_test_design.psp
...............\..\edg_test_design.pss
...............\..\edg_test_design.rpp.qmsg
...............\..\edg_test_design.rtlv.hdb
...............\..\edg_test_design.rtlv_sg.cdb
...............\..\edg_test_design.rtlv_sg_swap.cdb
...............\..\edg_test_design.sgate.rvd
...............\..\edg_test_design.sgate_sm.rvd
...............\..\edg_test_design.sgdiff.cdb
...............\..\edg_test_design.sgdiff.hdb
...............\..\edg_test_design.signalprobe.cdb
...............\..\edg_test_design.sld_design_entry.sci
...............\..\edg_test_design.sld_design_entry_dsc.sci
...............\..\edg_test_design.syn_hier_info
...............\..\edg_test_design.tan.qmsg
...............\..\edg_test_design.tis_db_list.ddb
...............\..\prev_cmp_edg_test_design.asm.qmsg
...............\..\prev_cmp_edg_test_design.fit.qmsg
...............\..\prev_cmp_edg_test_design.map.qmsg
...............\..\prev_cmp_edg_test_design.qmsg
...............\..\prev_cmp_edg_test_design.tan.qmsg
...............\edg_test_design.asm.rpt
...............\edg_test_design.bsf
...............\edg_test_design.done
...............\edg_test_design.fit.rpt
...............\edg_test_design.fit.smsg
...............\edg_test_design.fit.summary
...............\edg_test_design.flow.rpt
...............\edg_test_design.map.rpt
...............\edg_test_design.map.summary
...............\edg_test_design.pin
...............\edg_test_design.pof
...............\edg_test_design.qpf
...............\edg_test_design.qsf
...............\edg_test_design.qws
...............\edg_test_design.sof
...............\edg_test_design.tan.rpt
...............\edg_test_design.tan.summary
...............\edg_test_design.v
...............\edg_test_design.v.bak

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