VHDL-FPGA-Verilog List Page 1178

VHDL-FPGA-Verilog list

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mux2to1 Downloaded：0: - Press the learning board KEY1 key and the KEY2 key, LED lantern display the state- KEY3 as selector switch - 1 high level gating a channel signal is key1 0 low level strobe b Road signal is key2
Date : 2025-08-22 Size : 1kb User : lixiaolong
decoder3_8 Downloaded：0: - The output of the decoder is active low. So every time only a low level.- KEY1 and KEY2 key key and KEY3 key as A B C signal input. LED light output shows the default state of the state- the key is a high level - When
Date : 2025-08-22 Size : 1kb User : lixiaolong
add Downloaded：0: - A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3
Date : 2025-08-22 Size : 1kb User : lixiaolong
sub Downloaded：0: - A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3
Date : 2025-08-22 Size : 1kb User : lixiaolong
mlt Downloaded：0: - A0 a1 input we use the k1 k2 instead- b0 b1 input with k3 k4 instead- a digital display is 9. (11)* (11) is equivalent to 9- digital display subtracting the knot?
Date : 2025-08-22 Size : 1kb User : lixiaolong
dff1 Downloaded：0: - Learn the principles of the D flip-flop- Press the learning board of KEY1 key to display the status LED Lantern- press the button, the corresponding I/O is low. So LED lights?
Date : 2025-08-22 Size : 1kb User : lixiaolong
div_f Downloaded：0: - Learning divider principle, above the LED display.- The use of counter divider light up a dark 50MHZ frequency becomes slower. Our eyes can distinguish.- Output is 1Hz
Date : 2025-08-22 Size : 1kb User : lixiaolong
Xilinx-ISE-and-Modelsim Downloaded：0: Detailed Xilinx ISE and Modelsim joint simulation platform build process and a simple instance of the operating demonstration, illustrated, and have a very good platform to build
Date : 2025-08-22 Size : 1.58mb User : yangxin
Verilog-code Downloaded：0: Based on the source code of the cyclone kernel fpga, with quartus2, download files
Date : 2025-08-22 Size : 6.85mb User : hzx
micro-processor Downloaded：0: This the design of a 8-bit micro-processor.
Date : 2025-08-22 Size : 4kb User : baoshu
verilog Downloaded：0: opencore can bus verilog design file
Date : 2025-08-22 Size : 91kb User : zhixiaowen
siweijiafaqi Downloaded：0: Four-bit binary adder with four DIP switches four binary summand represents four binary addend another four DIP switches carry and display 5 digital tube.
Date : 2025-08-22 Size : 6kb User : 冯初晨

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