VHDL-FPGA-Verilog List Page 1174

VHDL-FPGA-Verilog list

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buzzer Downloaded：0: Buttons control the output signals of different frequencies to control the buzzer, using Verilog Programming
Date : 2025-08-21 Size : 48kb User : duan
dynamic_seg7 Downloaded：0: 7 digital tube dynamic display, using Verilog Programming
Date : 2025-08-21 Size : 261kb User : duan
decoder_3_8 Downloaded：0: 3-8 FPGA decoder in Verilog
Date : 2025-08-21 Size : 32kb User : duan
MT9M011_CCD Downloaded：0: DE2 image acquisition
Date : 2025-08-21 Size : 3.28mb User : dlj
clock_timer Downloaded：0: Clock, timer, 23 hours, 59 minutes, 59 seconds of clock, automatic binary timing, Verilog prepared
Date : 2025-08-21 Size : 56kb User : duan
digital-clock_VHDL Downloaded：0: use VHDL to build a digital clock, has been validated on FPGA
Date : 2025-08-21 Size : 5kb User : tufengbin
CPU Downloaded：0: Harbin Institute of Technology, computer professional, computer design and practical courses, CPU design
Date : 2025-08-21 Size : 5.98mb User : Advanced
SEG Downloaded：0: Using DE2 achieve the digital pipe incremental VERILOG
Date : 2025-08-21 Size : 1kb User : 金纯
VHDLmimasuo Downloaded：0: Reset the password function, password lock function, enter the clear function, alarm function, key switching function
Date : 2025-08-21 Size : 798kb User : 陈大伟
VHDLled Downloaded：0: VHDL design a " snake" figure eight in a row (four) seven-segment digital tube to beat about the bush, and through the buttons to change its direction of motion
Date : 2025-08-21 Size : 346kb User : 陈大伟
VHDLqiangdaqi Downloaded：0: Responder line test function, the First Responder signal the identification and latch function, foul warning function, timing, scoring function
Date : 2025-08-21 Size : 344kb User : 陈大伟
VHDLrsjiemaqi Downloaded：0: RS decoder design in China Mobile Multimedia Broadcasting
Date : 2025-08-21 Size : 509kb User : 陈大伟

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