VHDL-FPGA-Verilog List Page 1173

VHDL-FPGA-Verilog list

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VHDLtrafficlight Downloaded：0: Design of a traffic light, to commanding a crossroads of traffic under normal circumstances, red yellow and green three states, each green (red) lights for thirty seconds has emergencies keys, the road will remain for th
Date : 2025-08-21 Size : 309kb User : 陈大伟
ccd Downloaded：0: Of write a tcd1209d of timing-driven code, Verilog language, can learn from
Date : 2025-08-21 Size : 2kb User : 任慧建
ccd Downloaded：0: A ccd driver is written in verilog. Worth to learn.
Date : 2025-08-21 Size : 3kb User : 任慧建
SF-CY3-FPGA Downloaded：0: SF-CY3 FPGA Suite Developer' s Guide Ver3.00, students to learn is worth a look
Date : 2025-08-21 Size : 8.47mb User : 任慧建
4wire-driver-of-FPGA Downloaded：0: ALTERA Company hurricane ep2c5 with touch screen interface code.
Date : 2025-08-21 Size : 74kb User : amlin
CHENLI_VHDL_FINAL Downloaded：0: You will design a hexadecimal calculator.four push buttons represent Addition, Subtraction, Multiplication and Enter. There are also eight binary switches used to enter two operands for each calculation. The four digit h
Date : 2025-08-21 Size : 395kb User : Li Chen
two-of-the-state-machine-written Downloaded：0: The document introduces two of the state machine written- bristling write (write (in the incident to determine the state judge in the state in the event) and sideways).
Date : 2025-08-21 Size : 6kb User : 郑星
VHDLproject-by-Qian-Yu Downloaded：0: create a real-time video processor using FPGA technology in the course System Design with VHDL. In the project we implement modules for sliding window, sobel lter, a range sensor and a number displayer for VGA.
Date : 2025-08-21 Size : 2.19mb User : Li Chen
7segment-display-VHDL Downloaded：0: using the NEXYS 2 prototyping board Simulate the 7-segment encoder
Date : 2025-08-21 Size : 166kb User : Li Chen
adc0804 Downloaded：0: From the ADC0804' s channel IN+ analog input between 0 ~ 5V through ADC0804 conversion to digital, digital tube to decimal form is displayed.
Date : 2025-08-21 Size : 413kb User : 李庆龙
data_gen Downloaded：0: Generates random prbs sequence. For receiver testing. BER test wait
Date : 2025-08-21 Size : 1kb User : lexie
prbs Downloaded：0: verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
Date : 2025-08-21 Size : 1kb User : lexie

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