VHDL-FPGA-Verilog List Page 1052

VHDL-FPGA-Verilog list

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VHDL-DDS Downloaded：0: FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
Date : 2025-08-12 Size : 1kb User : 春雷
LED_test Downloaded：0: LED test about the testing of led on fpga
Date : 2025-08-12 Size : 399kb User : enlic
i2c_reg Downloaded：0: Using verilog achieve a slave I2C communication module, the test is available, has been used in the project!
Date : 2025-08-12 Size : 3kb User : linhanxiong
Timing_Constraints_and_Optimization Downloaded：0: SYSNOSYS company gives back timing analysis on digital information, for learning digital design has a very big help, speak very comprehensive
Date : 2025-08-12 Size : 1.97mb User : linhanxiong
Timing Downloaded：0: Abroad on timing design of a very good book, written in great detail, including the principle of timing analysis, etc.
Date : 2025-08-12 Size : 5.28mb User : linhanxiong
usrp-fpga-mirror Downloaded：0: usrp1 of the FPGA source code, need to be studies
Date : 2025-08-12 Size : 19.21mb User : wangpoba
VHDL-and-Verilog Downloaded：0: verilog and vhdl language into each other, there are algorithms and source code, help students learn FPGA
Date : 2025-08-12 Size : 8.03mb User : 朱孔
DataSignal Downloaded：0: Parallel serial data transmission and reception, the final output parallel data, the middle even parity bit, alarm bit, the receiver for receiving data even parity, correct reception, there are problems then the police.
Date : 2025-08-12 Size : 339kb User : 张晓溪
HEX8 Downloaded：0: Description of seven-segment digital tube circuit, the normal decoding function, and patients into integrated 8 digital control module
Date : 2025-08-12 Size : 1kb User : lubo2288
SD_Text Downloaded：0: Nois iiSD-LCM-based electronic album IDE IP soft core control program
Date : 2025-08-12 Size : 4kb User : madoudou
cpu8bit Downloaded：0: This a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.
Date : 2025-08-12 Size : 759kb User : 陈飞飞
up_down_counter Downloaded：0: the code is written by verilog HDL, and present a kind of up-down counter to realize triangle carrier
Date : 2025-08-12 Size : 418kb User : 宫杰

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