CodeBus
www.codebus.net
Search
Sign in
Sign up
Hot Search :
Source
embeded
web
remote control
p2p
game
More...
Location :
Home
SourceCode
Embeded-SCM Develop
VHDL-FPGA-Verilog
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Search in result
Search
VHDL-FPGA-Verilog list
Sort by :
«
1
2
...
.44
.45
.46
.47
.48
1049
.50
.51
.52
.53
.54
...
4310
»
基于MIPS指令集的五级流水线
Downloaded:0
运用verilog语言实现的MIPS指令集,包括加、减、比较、与、异或等指令。运用五级流水线,设置IF,ID,EX,MEM、WB五个栈间计算模块。运用了forwarding和stop技术。可以使用modelsim验证。
Date
: 2013-07-03
Size
: 138.25kb
User
:
cjc87267137
DES算法的verilog实现
Downloaded:0
用verilog实现的DES算法。模块划分详细。可以用modelsim验证。
Date
: 2013-07-03
Size
: 100.64kb
User
:
cjc87267137
JK-flip-flop
Downloaded:0
Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
Date
: 2025-08-12
Size
: 15kb
User
:
chen
spi_interface_premier_slave
Downloaded:0
verilog version of the spi interface slaver part of the program
Date
: 2025-08-12
Size
: 1kb
User
:
齐天大圣
traffic
Downloaded:0
A simple traffic light controller, traffic lights display module test box to display the traffic lights. System clock selection 1Hz clock module clock, flashing yellow clock 1Hz, the red light 15s, yellow light 5s, green
Date
: 2025-08-12
Size
: 1.44mb
User
:
李建国
chaoqianjinweiliuweijiafaqi
Downloaded:0
6 bit Adder
Date
: 2025-08-12
Size
: 33kb
User
:
nick
ll_clock
Downloaded:0
Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital clock time reference, and then passes through a divider output standard second pulse. Second counter at least 60 mi
Date
: 2025-08-12
Size
: 1.43mb
User
:
李建国
ALU
Downloaded:0
verilog prepared eight ALU, subtract, or compare with
Date
: 2025-08-12
Size
: 2kb
User
:
姬成
divider_testbench_vhdl_611508553
Downloaded:0
Divider testbench test
Date
: 2025-08-12
Size
: 1kb
User
:
姬成
alu_testbench_vhdl_689102300
Downloaded:0
The ALU testbench test can be co-simulation using
Date
: 2025-08-12
Size
: 1kb
User
:
姬成
SONGER
Downloaded:0
ABEL language use to design a multi-mode counter, the experimental stage 100KHz dividing to produce eight kinds of the desired frequency. The eight kinds of frequency loudspeaker signal input to produce eight different s
Date
: 2025-08-12
Size
: 2.01mb
User
:
李建国
EDA_2
Downloaded:0
Simple calculator four also showed that addition and subtraction with instructions
Date
: 2025-08-12
Size
: 28kb
User
:
姬成
«
1
2
...
.44
.45
.46
.47
.48
1049
.50
.51
.52
.53
.54
...
4310
»
CodeBus
is one of the largest source code repositories on the Internet!
Contact us :
1999-2046
CodeBus
All Rights Reserved.