VHDL-FPGA-Verilog List Page 1035

VHDL-FPGA-Verilog list

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Enc_With_Punc---2011-11-28-v3.0 Downloaded：0: Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
Date : 2025-08-12 Size : 2.38mb User :
ceping1 Downloaded：0: FPGA-based design a frequency counter, and I hope there is a need to help friends. It is simply a thing, I hope everyone Improved!
Date : 2025-08-12 Size : 1.92mb User : 王凌
I2C_slavemodule Downloaded：0: Verilog I2C TO spi code
Date : 2025-08-12 Size : 1.85mb User :
rs_204_188----v1.0 Downloaded：1: RS Coding and Decoding Verilog code，　implement RS（204,188)
Date : 2025-08-12 Size : 2.23mb User : zhufull
uartverilog Downloaded：0: VERILOG HDL to write serial driver, proven functionality can normally achieve serial
Date : 2025-08-12 Size : 4.97mb User : 余小新
FPGA-BASYS2 Downloaded：0: Development board based on FPGA BASYS2 digital clock, to achieve timing, time calibration, alarm, hourly chime functions.
Date : 2025-08-12 Size : 4kb User : 何畅
FPGA-a-CPLD-kaifajingyan Downloaded：0: Hard to come by FPGA and CPLD development experience
Date : 2025-08-12 Size : 928kb User : zouyong
nspwm Downloaded：0: 用fpga生产SPWM波形稳定，输出频率占空比可调。
Date : 2013-07-17 Size : 2.44mb User : jackoxiong
nspwm Downloaded：0: Function: generate SPWM waveform, frequency, duty cycle adjustable, the output waveform is stable.
Date : 2025-08-12 Size : 2.44mb User : adrian
spwm2 Downloaded：0: SPWM waveform generated by fpga, the output waveform is stable, adjustable duty cycle frequency.
Date : 2025-08-12 Size : 3.23mb User : adrian
Music_Player Downloaded：0: Verilog-based music player program, in Modelsim6.5 through simulation and can be run on the development board
Date : 2025-08-12 Size : 2.26mb User : 朱恒
seven-segment-decoder Downloaded：0: Simple seven-segment decoder verilogDHL code although very simple but hope to learn more things that
Date : 2025-08-12 Size : 55kb User : tang

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