VHDL-FPGA-Verilog List Page 1039

VHDL-FPGA-Verilog list

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brom_16x8 Downloaded：0: ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
Date : 2025-08-12 Size : 7kb User : 于洋
bram_16x8_top Downloaded：0: RAM using Verilog language program, you can bi-literacy, in the Xilinx Spartan-6 run through, is a very good program Verlog
Date : 2025-08-12 Size : 9kb User : 于洋
two_dimension_fpga Downloaded：0: FPGA Implementation of Fuzzy Control
Date : 2025-08-12 Size : 723kb User : 张颖
uart Downloaded：0: The uart communication design based wishbone
Date : 2025-08-12 Size : 24kb User : 赵奥飞
static-timing-analyze Downloaded：0: Speaker privileged classmates timing constraints for FPGA design topics (STA section)
Date : 2025-08-12 Size : 996kb User : 张炽
altera Downloaded：0: For serial and fiber optic communications, in 232, and 485 and the light switching, requires adaptive algorithms.
Date : 2025-08-12 Size : 3.46mb User : 杨志鹏
EP2C70F896C6N-pins Downloaded：0: VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions
Date : 2025-08-12 Size : 408kb User : zyq
phase_measure Downloaded：0: This a calculation of two signals of the same type of implementation of the code phase of the Verilog
Date : 2025-08-12 Size : 1kb User : 陈庆
SLAVE-FIFO-8BITS Downloaded：0: EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
Date : 2025-08-12 Size : 1.6mb User : Eddie
XC3S700_HS_SDRAM Downloaded：0: Red Hurricane 3S700AN development board SDRAM test code
Date : 2025-08-12 Size : 2.07mb User : Eddie
XC3S700_UART_Test Downloaded：0: Red Hurricane 3S700AN development board UART test code
Date : 2025-08-12 Size : 1.76mb User : Eddie
XC3S700_LCD_Test Downloaded：0: Red Hurricane 3S700AN LCD development board test code
Date : 2025-08-12 Size : 711kb User : Eddie

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