VHDL-FPGA-Verilog List Page 1033

VHDL-FPGA-Verilog list

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UART_VERILOG Downloaded：0: The program in ALTERA FPGA VERILOG HDL language used on serial communication.
Date : 2025-08-12 Size : 3kb User : ccy
sram_test Downloaded：0: is61lv25616 simple verilog program, complete sram read and write
Date : 2025-08-12 Size : 1kb User : yang
tlc549 Downloaded：0: Use tlc549 achieve ad transform and led on display
Date : 2025-08-12 Size : 9kb User : 李永超
YIWEIJICUNQI Downloaded：0: Two kinds of shift register design, namely, universal shift register with the barrel shifter
Date : 2025-08-12 Size : 1kb User : 李永超
CHUANKOU Downloaded：0: Through the clock divider, and a serial port receive and transmit serial debugging procedures for the preparation of the receiving and sending data
Date : 2025-08-12 Size : 3kb User : 李永超
shixuzhuangtaiji Downloaded：0: By verilog hdl language for writing timing state machine
Date : 2025-08-12 Size : 1kb User : 李永超
JIFENLBOQI Downloaded：0: By verilog hdl language used to complete the design of the integrator comb filter
Date : 2025-08-12 Size : 1kb User : 李永超
RS Downloaded：0: Verilog hdl language through the RS encoder and decoder design
Date : 2025-08-12 Size : 26kb User : 李永超
chengfaqi Downloaded：0: By verilog hdl language Galois field GF (q) Multiplier
Date : 2025-08-12 Size : 2kb User : 李永超
SUANSHUJISUAN Downloaded：0: Achieved through verilog hdl adder multiplier, divider design
Date : 2025-08-12 Size : 5kb User : 李永超
data Downloaded：0: Verilog hdl achieved through the comparison of the data, the distributor selection
Date : 2025-08-12 Size : 6kb User : 李永超
Digital-clock Downloaded：0: Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function
Date : 2025-08-12 Size : 490kb User : 苏婧

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