VHDL-FPGA-Verilog List Page 1029

VHDL-FPGA-Verilog list

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Lab2_Part1 Downloaded：0: display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Date : 2025-08-12 Size : 25kb User : Henna Tan
Lab2_Part2 Downloaded：0: converts a 4-bit binary code to 2-digital BCD code in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Date : 2025-08-12 Size : 110kb User : Henna Tan
part1 Downloaded：0: a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Date : 2025-08-12 Size : 137kb User : Henna Tan
436394195AlteraFPGA Downloaded：0: FPGA development board schematics, Hurricane II FPGA board Schematic Library
Date : 2025-08-12 Size : 1.64mb User : 邓辉超
integrative-concept Downloaded：0: This book is about the concept of integration verilog language, verilog language is the essence of organized combing is recommended reading.
Date : 2025-08-12 Size : 4.2mb User : 陈波
verilog-Literacy Downloaded：0: As the name implies, this is a beginner literacy verilog text. Content easy to understand, so you are full of interest in learning.
Date : 2025-08-12 Size : 3.18mb User : 陈波
DE2_CAMERA Downloaded：0: DE2 board CMOS camera image acquisition program.
Date : 2025-08-12 Size : 4.79mb User : xigua
VGA_Display Downloaded：0: VGA interface based on Verilog language program, including VGA interface timing control, and pattern generation module.
Date : 2025-08-12 Size : 206kb User : xigua
shuzizhong Downloaded：0: Digital clock stopwatch and alarm clock
Date : 2025-08-12 Size : 2.04mb User : 曾昶畅
VGA-RefComp Downloaded：0: Implemented in the development board Basys2 VGA interface design, which in Basys2 development platform tested, there is no problem
Date : 2025-08-12 Size : 108kb User : xiao
ml605_FMC_Si570_Prog_rdf0047_13.4_c Downloaded：0: The source is based on xilinx ml605 development board FMC expansion interface design, the development board daughter card is inserted, the program development board test.
Date : 2025-08-12 Size : 27.19mb User : xiao
ml605_MIG_rdf0011_13.4_c Downloaded：0: The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
Date : 2025-08-12 Size : 16.52mb User : xiao

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