VHDL-FPGA-Verilog List Page 1021

VHDL-FPGA-Verilog list

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DDS Downloaded：0: DDS signal source to achieve source
Date : 2025-08-12 Size : 34kb User : 张继森
1602Pkeyscan Downloaded：0: FPGA-based lcd1602 and matrix key scanning program (verilog)
Date : 2025-08-12 Size : 1.66mb User : 文杰
filter Downloaded：0: Filter through modelsim simulation get the correct result
Date : 2025-08-12 Size : 2kb User : 刘媛媛
shumaguan Downloaded：0: Various digital display source, segment, eight out of a total of yin yang are, and have been to get the correct waveform simulation
Date : 2025-08-12 Size : 1kb User : 刘媛媛
dingshi Downloaded：0: Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct
Date : 2025-08-12 Size : 1kb User : 刘媛媛
count Downloaded：0: Various common counter module, subtraction controllable variable modulus counter counter and so on, through simulation to get the correct waveform
Date : 2025-08-12 Size : 4kb User : 刘媛媛
duoji Downloaded：0: FPGA-based, using Verilog language, through the detection of black lines to control the steering process.
Date : 2025-08-12 Size : 339kb User : 姜敏敏
8051based_on_Verilog Downloaded：0: 8051 core verilog achieve
Date : 2025-08-12 Size : 247kb User : 黄浚羽
Structural-UpDown-Counter Downloaded：0: Structural UpDown Counter
Date : 2025-08-12 Size : 1kb User : hadimk
RAMFIFO_Ctrl_LFSR Downloaded：0: RAMFIFO with LFSR Controller
Date : 2025-08-12 Size : 5kb User : hadimk
DistRAM Downloaded：0: Distributed Single Port RAM
Date : 2025-08-12 Size : 2kb User : hadimk
FCS_16 Downloaded：0: Frame Check Sequence 16 bit Generator (CRC-CCITT and CRC-16)
Date : 2025-08-12 Size : 2kb User : hadimk

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