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VHDL-FPGA-Verilog list
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fpga_dds
Downloaded:0
Design a direct digital frequency synthesis (DDS, Direct Digital Synthesis), DDS is a kind of new type of frequency synthesis technologies. DDS technology is a way to series of digital form signals, through the DAC conve
Date
: 2025-08-12
Size
: 1mb
User
:
KCHEN
Multiplier-code-with-testbench
Downloaded:0
VHDL code for synthesizable Multiplier with testbench
Date
: 2025-08-12
Size
: 1kb
User
:
Tamoghna Purkaystha
display
Downloaded:0
seven segment display apllication with only one push button up counter
Date
: 2025-08-12
Size
: 42kb
User
:
resul koksal
flash
Downloaded:0
fpga nios ii vhdl qsys
Date
: 2025-08-12
Size
: 3.71mb
User
:
xuwenqing
filter_lpm_shaping
Downloaded:0
4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
Date
: 2025-08-12
Size
: 16.19mb
User
:
chen
uart
Downloaded:0
A practical uart protocol modules, use verilog to achieve
Date
: 2025-08-12
Size
: 1kb
User
:
lzc
myuart
Downloaded:0
Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
Date
: 2025-08-12
Size
: 481kb
User
:
夏小保
uart
Downloaded:0
uart Verilog code, no problem tested, the test file
Date
: 2025-08-12
Size
: 623kb
User
:
gao
LCD-NH12864J-VHDL
Downloaded:0
LCD NH12864J Controler Prog examples
Date
: 2025-08-12
Size
: 534kb
User
:
房有定
FT245BL_test
Downloaded:0
this a example for the mouse vga for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
Date
: 2025-08-12
Size
: 17kb
User
:
Darshana tharanga
mod10counter
Downloaded:0
Implemented using D flip-flop mode 10 counters, Xilinx14.4ISE compiled by
Date
: 2025-08-12
Size
: 385kb
User
:
chennanxu
VHDL-code-specification
Downloaded:0
vhdl code specifications. Including naming, such statements use. Attention to portability and hardware resource conservation.
Date
: 2025-08-12
Size
: 729kb
User
:
Bai
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