8051 core verilog achieve

8051的Verilog源代码\asm\test.asm
...................\bench\verilog\oc8051_defines.v
...................\.....\.......\oc8051_fpga_tb.v
...................\.....\.......\oc8051_tb.v
...................\.....\.......\oc8051_timescale.v
...................\rtl\verilog\oc8051_acc.v
...................\...\.......\oc8051_alu.v
...................\...\.......\oc8051_alu_src1_sel.v
...................\...\.......\oc8051_alu_src2_sel.v
...................\...\.......\oc8051_alu_src3_sel.v
...................\...\.......\oc8051_comp.v
...................\...\.......\oc8051_cy_select.v
...................\...\.......\oc8051_decoder.v
...................\...\.......\oc8051_defines.v
...................\...\.......\oc8051_divide.v
...................\...\.......\oc8051_dptr.v
...................\...\.......\oc8051_ext_addr_sel.v
...................\...\.......\oc8051_fpga_tb.v
...................\...\.......\oc8051_fpga_top.v
...................\...\.......\oc8051_immediate_sel.v
...................\...\.......\oc8051_indi_addr.v
...................\...\.......\oc8051_multiply.v
...................\...\.......\oc8051_op_select.v
...................\...\.......\oc8051_pc.v
...................\...\.......\oc8051_port_out.v
...................\...\.......\oc8051_psw.v
...................\...\.......\oc8051_ram_rd_sel.v
...................\...\.......\oc8051_ram_sel.v
...................\...\.......\oc8051_ram_sel1.v
...................\...\.......\oc8051_ram_top.v
...................\...\.......\oc8051_ram_top1.v
...................\...\.......\oc8051_ram_wr_sel.v
...................\...\.......\oc8051_reg1.v
...................\...\.......\oc8051_reg2.v
...................\...\.......\oc8051_reg3.v
...................\...\.......\oc8051_reg4.v
...................\...\.......\oc8051_reg5.v
...................\...\.......\oc8051_reg8.v
...................\...\.......\oc8051_rom_addr_sel.v
...................\...\.......\oc8051_sp.v
...................\...\.......\oc8051_tb.v
...................\...\.......\oc8051_timescale.v
...................\...\.......\oc8051_top.v
...................\...\.......\oc8051_top1.v
...................\...\.......\read.me
...................\sim\rtl_sim\out\VERILOG.LOG
...................\...\.......\run\MAKE
...................\...\.......\...\make_fpga
...................\...\.......\src\verilog\oc8051_ram.v
...................\...\.......\...\.......\oc8051_rom.v
...................\.yn\log\oc8051_top.srr
...................\...\out\oc8051.ucf
...................\...\...\oc8051_top.bit
...................\...\...\oc8051_top.srm
...................\...\...\oc8051_top.srs
...................\...\...\read.me
...................\...\src\verilog\disp.v
...................\...\...\.......\oc8051_fpga_top.v
...................\...\...\.......\oc8051_ram.v
...................\...\...\.......\oc8051_rom.v
...................\...\...\.......\read.me
...................\.im\rtl_sim\src\verilog
...................\...\.......\out
...................\...\.......\run
...................\...\.......\src
...................\.yn\src\verilog
...................\bench\verilog
...................\rtl\verilog
...................\sim\rtl_sim
...................\.yn\log
...................\...\out
...................\...\src
...................\asm
...................\bench
...................\rtl
...................\sim
...................\syn
8051的Verilog源代码

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