Search - virtex II

[Other resource] PCI_target

Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: | Size: 845501 | Author: citybus | Hits:

[Other resource] pingpufx

Description: 本设计以凌阳16位单片机SPCE061A为核心控制器件，配合Xilinx Virtex-II FPGA及Xilinx公司提供的硬件DSP高级设计工具System Generator，制作完成本数字式外差频谱分析仪。前端利用高性能A/D对被测信号进行采集，利用FPGA高速、并行的处理特点，在FPGA内部完成数字混频，数字滤波等DSP算法。
Platform: | Size: 258459 | Author: 郑坤 | Hits:

[Other resource] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。
Platform: | Size: 8431602 | Author: 杨奋燕 | Hits:

[Other resource] KCPSM3

Description: This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze
Platform: | Size: 1513756 | Author: 王斯弘 | Hits:

[VHDL-FPGA-Verilog] PCI_target

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[VHDL-FPGA-Verilog] KCPSM3

Description: This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze -This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devicesby Picoblaze
Platform: | Size: 1513472 | Author: 王斯弘 | Hits:

[VHDL-FPGA-Verilog] XilinxisdisclosingthisSpecification

Description: Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C64x EMIF 连接到 Virtex-4 FPGA 的实现。 ? 第 4 章“参考设计” 提供参考设计的目录结构和参考设计文件的链接。 ? 附录 A “Virtex-4 ISERDES 样本代码” 提供 Virtex-4 实现的样本代码列表。 ? 附录 B “EMIF 寄存器域描述” 定义 TI DSP 寄存器域。 ? 附录 C “相关参考文件” 提供相关文档的链接-Xilinx is disclosing this Specification? Chapter 1
Platform: | Size: 669696 | Author: xujj | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Xilinx可编程逻辑器件的高级应用与设计技巧全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to Xilinx s CoolRunnerII Spartan-3 Virtex-II VirtexII pro, such as the structural characteristics of the device, as well as its ISE6-aided design tools.
Platform: | Size: 41021440 | Author: 胡赟星 | Hits:

[VHDL-FPGA-Verilog] soc-OverviewProcessors.pdf

Description: 几款处理器相互比较，包括EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)-OVERVIEW-EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)
Platform: | Size: 292864 | Author: piansu | Hits:

[VHDL-FPGA-Verilog] wtut_sc

Description: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Platform: | Size: 106496 | Author: shad | Hits:

[Software Engineering] FPGA_DSP

Description: Virtex-II Pro _ Virtex-II Pro X 完整数据手册(包含全部4个模块)；XtremeDSP开发套件Pro用户指南；及如何利用ML300 Virtex-II Pro开发系统着手开始搭建系统。-Virtex-II Pro _ Virtex-II Pro X Full Data Sheet (includes all four modules) XtremeDSP Development Kit Pro User Guide and how to use the ML300 Virtex-II Pro Development System getting started to build the system.
Platform: | Size: 7115776 | Author: 福东方 | Hits:

[Linux-Unix] Virtex_II_Pro_LINUX

Description: 在XILINX Virtex-II Pro Development Board开发板上移植LINUX系统-Porting MontaVista Linux to the XUP Virtex-II Pro Development Board
Platform: | Size: 3467264 | Author: horse | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[Software Engineering] VHDL_RAM

Description: Virtex II pro RAM memory
Platform: | Size: 8192 | Author: Paco | Hits:

[Software Engineering] DesignandFPGAImplementationof

Description: In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero frequencies completely. Using the “Vlach-Chebyshev approximation” [1] however, we are able to specify the (Chebyshev) passband limits directly, together with a free choice of transfer zero locations in the stopband. In this way it is possible to design bandpass transfer functions that cannot be obtained from lowpass functions by a frequency transformation. We think this method to be the only (and not very well known) analytical method to obtain such bandpass characteristics. We show how we designed wave digital realizations from the specification, through a VHDL description and synthesis into a Xilinx FPGA (Virtex-II).
Platform: | Size: 195584 | Author: rakesh | Hits:

[VHDL-FPGA-Verilog] Xilinx_question

Description: ：ISE5.1i是Xilinx推出的具有ASIC-strength的设计工具，它充分发掘了VirtexⅡPro系列芯片的潜力；Virtex-II Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比，设计人员在编译时所花的时间得到了成倍提高（从100,000/min增加到200,000门/min）并且在器件速度上增加了40 。-: ISE5.1i is a Xilinx introduced a ASIC-strength design tools, which fully exploit the Virtex Ⅱ Pro series chip' s potential Virtex-II Pro series of chip gate density of 40,000 to 8,000,000 from the door. Compared with the 4.1i, the designer at compile time, the time spent has been improved several times (from 100,000/min to 200,000 gate/min) and in the device speed increase of 40 .
Platform: | Size: 103424 | Author: backoff | Hits:

[VHDL-FPGA-Verilog] xapp866

Description: 用于 Texas Instruments 模数转换器的 Virtex-4 和 Virtex-5 接口-Texas Instruments ADC for Virtex-4 and Virtex-5 Interface
Platform: | Size: 13414400 | Author: 刘烈超 | Hits:

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