ddr_sdr_V1_1 DR SDRAM Controller Core - has been d

Title: ddr_sdr_V1_1

Category:
VHDL-FPGA-Verilog
Tags:
[Text]
File Size:
37kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
jordanliang2005

Description: DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device

Downloaders recently: [More information of uploader jordanliang2005]

To Search: DDR FPGA ddr xilinx ddr DDR II VHDL DDR

[very-good-ok-ref-ddr-sdram-verilog] - Sdr SDRAM controller reference design, v
[ddr_sdr_V1_1] - ddr verilog code, realize DDR memory con
[DDR] - DDR SDRAM on detailed principles and tim
[DDR_SDRAM_controller] - DDR SDRAM controller VHDL source code, i
[DDR_SDRAM] - DDR RAM controller VHDL source code, the
[xapp860] - 16-Channel, DDR LVDS Interface with Real
[ddr-sdram--chengxu] - ddr
[sdram] - Procedure Note: In this experiment, cont
[ddr_contrl] - DDR controller source code and test benc
[s3edisp_schem] - This document is a entire schematic of S

File list (Check if you may need any files):

ddr_sdr_V1_1
............\ddr_dcm.vhd
............\ddr_sdr.ucf
............\ddr_sdr.vhd
............\ddr_sdr_conf_pkg.vhd
............\license.dat
............\mt46v16m16.vhd
............\readme.txt
............\reset.vhd
............\tb.vhd
............\user_if.vhd

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net