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[VHDL-FPGA-Verilog] VHDL-status DL : 0: VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Date : 2025-07-12 Size : 6kb User : 陈度甫
[VHDL-FPGA-Verilog] vhdl-examples DL : 0: 这是eda初学者可以借鉴的两个关于电子频率计的VHDL设计实例-This is the EDA beginners can learn from two of electronic Cymometer VHDL Design Example
Date : 2025-07-12 Size : 11kb User : 刘磊
[VHDL-FPGA-Verilog] VHDL-six DL : 0: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Date : 2025-07-12 Size : 25kb User : philohb
[Crack Hack] 3des-VHDL DL : 0: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Date : 2025-07-12 Size : 93kb User : xin
[VHDL-FPGA-Verilog] VHDL.fifo DL : 0: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Date : 2025-07-12 Size : 1.12mb User : 黎莉
[VHDL-FPGA-Verilog] fir-vhdl DL : 0: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Date : 2025-07-12 Size : 5kb User : MAX
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Date : 2025-07-12 Size : 122kb User :
[Software Engineering] cpu-16-vhdl DL : 0: 16位cpu的vhdl源代码。自己看看，没有注释。-16 cpu vhdl the source code. See for yourself, not Notes.
Date : 2025-07-12 Size : 93kb User : 童宗挺
[VHDL-FPGA-Verilog] DS18B20+VHDL DL : 0: 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
Date : 2025-07-12 Size : 799kb User : 刘西圣
[Software Engineering] (7)VHDL DL : 0: 是老师介绍的一些关于vhdl设计的源程序及讲解，感觉还不错，要不你们-teachers on the design of some of the source code vhdl and briefings, the feeling was pretty good, you want to try
Date : 2025-07-12 Size : 556kb User : 张松
[Software Engineering] VHDL DL : 0: 基才VHDL状态机设计的智能交通控制灯设计有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
Date : 2025-07-12 Size : 136kb User : 杨树茂
[Books] VHDL DL : 0: 基才VHDL状态机设计的智能交通控制灯有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to see what
Date : 2025-07-12 Size : 255kb User : 杨树茂
[VHDL-FPGA-Verilog] mc8051-VHDL DL : 0: VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
Date : 2025-07-12 Size : 600kb User : 陈同
[Graph program] DCT-vhdl DL : 0: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Date : 2025-07-12 Size : 10kb User : liujl
[Software Engineering] VHDL DL : 0: vhdl语言设计资料，学习FPGA设计的好书籍。-vhdl脫茂脩脭脡猫录脝脳脢脕脧拢卢脩搂脧掳 FPGA脡猫录脝渭脛潞脙脢茅录庐隆拢
Date : 2025-07-12 Size : 1.52mb User : 闫胜利
[Other] VHDL DL : 0: VHDL经典讲义，ppt格式的。可作为教材试用，挺好的-err
Date : 2025-07-12 Size : 391kb User : bibi
[Software Engineering] filter-vhdl-code DL : 0: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, including an integrated code. Use version ISE6.3.
Date : 2025-07-12 Size : 169kb User : petri
[Other] VHDL DL : 0: 一本很好的关于VHDL硬件描述语言方面的书籍，个人觉得写得还不错。-A very good on the VHDL hardware description language books, written personally feel that good.
Date : 2025-07-12 Size : 17.83mb User : 柳余恨
[VHDL-FPGA-Verilog] VHDL-vga_core(vhdl) DL : 0: VHDL-vga_core(vhdl).rar FPGA上实现 VGA的IP（VHDL）-VHDL-vga_core (vhdl). RarFPGA realize VGA on the IP (VHDL)
Date : 2025-07-12 Size : 448kb User : nanotalk
[VHDL-FPGA-Verilog] PS2-IP-CORE-VHDL DL : 0: 一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA
Date : 2025-07-12 Size : 26kb User : nanotalk

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