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[Other Embeded program] verilog source

Description: verilog的源代码。给出来常用的一些例程，对于verilog的使用和学习都有很大的帮助作用。-Verilog source code. Out to some routines commonly used for the use and Verilog study has been very helpful.
Platform: | Size: 176128 | Author: 林伟 | Hits:

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369664 | Author: 陈俊 | Hits:

[VHDL-FPGA-Verilog] 用Verilog HDL实现I2C总线功能

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Platform: | Size: 120832 | Author: 胡路听 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4096 | Author: 张雷 | Hits:

[VHDL-FPGA-Verilog] des-verilog

Description: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Platform: | Size: 67584 | Author: 杨云丰 | Hits:

[Other] 《Verilog黄金指南》中文翻译版

Description: Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法-Verilog learning materials, they simply PLD development language, and to highlight the key Verilog syntax
Platform: | Size: 468992 | Author: 张 | Hits:

[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶

Description: 初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information
Platform: | Size: 680960 | Author: chencsw | Hits:

[VHDL-FPGA-Verilog] hjs Verilog

Description: 是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
Platform: | Size: 39936 | Author: 黄先生 | Hits:

[VHDL-FPGA-Verilog] Verilog DHL数字钟

Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Platform: | Size: 2048 | Author: 谢树扬 | Hits:

[Books] A Verilog HDL Test Bench Primer

Description: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Platform: | Size: 57344 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback- shift-register
Platform: | Size: 2048 | Author: 陈正一 | Hits:

[Books] Verilog Modeling

Description: verilog语言建模资料，从网上整理的，-Verilog language modeling information collated from the Internet.
Platform: | Size: 7168 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] verilog实例

Description: 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
Platform: | Size: 165888 | Author: 叶若寒 | Hits:

[VHDL-FPGA-Verilog] Verilog-statemachine

Description: 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
Platform: | Size: 183296 | Author: 张厂 | Hits:

[Other] Verilog-r2-wangzhengxiong

Description: 学些verilog语言的入门书籍，由汪正雄编写，内容挺全的，可以作为初学者的手册。-up some Verilog language entry books, prepared by Hongzhengxiong, as Ting-wide and can serve as a beginner's manual.
Platform: | Size: 401408 | Author: | Hits:

[Other] arm7-verilog

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 37888 | Author: 王云 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: | Size: 784384 | Author: 东子 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] verilog-som

Description: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Platform: | Size: 5120 | Author: 刘索山 | Hits:
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