Search - verilog

[source in ebook] verilog

Description: 数字信号处理的FPGA实现(Uwe Meyer-Baese)书中例子的Verilog代码-FPGA implementation of digital signal processing (Uwe Meyer-Baese) book example of Verilog code for
Platform: | Size: 330752 | Author: lin | Hits:

[Energy industry] Verilog

Description: 全加器的Verilog 实现代码寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Platform: | Size: 3072 | Author: 田静 | Hits:

[VHDL-FPGA-Verilog] verilog-counter

Description: 利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
Platform: | Size: 2048 | Author: xzd | Hits:

[VHDL-FPGA-Verilog] syn-fifo-verilog

Description: 用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
Platform: | Size: 100352 | Author: runxin218 | Hits:

[VHDL-FPGA-Verilog] sdram-control-verilog

Description: SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
Platform: | Size: 991232 | Author: runxin | Hits:

[Special Effects] RGB2YUV(Verilog)

Description: YUV颜色空间转RGB颜色空间,verilog代码实现-YUV to RGB,verilog
Platform: | Size: 2048 | Author: 蔡玉强 | Hits:

[Other] verilog

Description: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Platform: | Size: 17408 | Author: ddr | Hits:

[Other] Verilog

Description: 无线通信FPGA书籍中的 Verilog代码-the code of the Verilog in the book-wireless communications FPGA
Platform: | Size: 131072 | Author: 夏宝平 | Hits:

[VHDL-FPGA-Verilog] chengfa-verilog

Description: booth乘法器verilog代码.利用移位和加法来实现乘法-verilog
Platform: | Size: 141312 | Author: 王林 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: Verilog 经典教程初学者必备。很经典的教程-Verilog classic essential tutorial for beginners.
Platform: | Size: 1307648 | Author: lli | Hits:

[VHDL-FPGA-Verilog] VERILOG-jpeg

Description: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Platform: | Size: 103424 | Author: ken | Hits:

[Software Engineering] Verilog

Description: Verilog语言学习资料，希望对给为有一点帮助哈-Verilog language learning materials, hoping to have some help on to Kazakhstan
Platform: | Size: 593920 | Author: 周心驰 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: Verilog-HDL实践与应用系统设计-Verilog-HDL Practice and Application System Design
Platform: | Size: 15430656 | Author: 李秀艳 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《北航常晓明Verilog应用》一书的pdf完整版，是学习Verilog的好书-" Beihang Chang Xiaoming Verilog Applications" pdf full version of the book is a good book to learn Verilog
Platform: | Size: 15432704 | Author: 甘福连 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Platform: | Size: 4096 | Author: 张霄 | Hits:

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[source in ebook] verilog

[Energy industry] Verilog

[VHDL-FPGA-Verilog] verilog-counter

[VHDL-FPGA-Verilog] syn-fifo-verilog

[VHDL-FPGA-Verilog] sdram-control-verilog

[Special Effects] RGB2YUV(Verilog)

[Other] verilog

[Other] Verilog

[VHDL-FPGA-Verilog] chengfa-verilog

[VHDL-FPGA-Verilog] Verilog

[VHDL-FPGA-Verilog] VERILOG-jpeg

[Software Engineering] Verilog

[VHDL-FPGA-Verilog] Verilog-HDL

[VHDL-FPGA-Verilog] Verilog-HDL

[VHDL-FPGA-Verilog] verilog

[Communication] verilog

[Other] verilog-ieee2001

[source in ebook] verilog

[Other] ddr-sdram-verilog-resource

[VHDL-FPGA-Verilog] Verilog

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