Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - rs encoder vhdl

Search list

[Other resource] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 77351 | Author: 王文 | Hits:

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[Communication-Mobile] RSencoder

Description: 关于rs码编码器的相关程序，利用硬件语言实现-Rs encoder code on the relevant procedures, take advantage of the hardware language
Platform: | Size: 5120 | Author: 庄镒鹏 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[VHDL-FPGA-Verilog] RS

Description: reed selemon encoder vhdl code
Platform: | Size: 77824 | Author: mohamed saad | Hits:

[VHDL-FPGA-Verilog] RS_ENCODER

Description: DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
Platform: | Size: 3072 | Author: sun mingang | Hits:

[Other] venomgen

Description: venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench generation
Platform: | Size: 258048 | Author: Michael Lau | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
Platform: | Size: 897024 | Author: lcz | Hits:

[Program doc] RS3123

Description: Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its random and unexpected error has a strong error correction capabilities, widely used in digital video broadcasting (DVB) systems and other digital communications. Gives a GF (25) Domains RS (31, 23) algorithm of the encoder is introduced with a Field Programmable Gate Array (FPGA) RS encoder to achieve the principles and processes, and providing a circuit and simulation of the output waveform.
Platform: | Size: 360448 | Author: 王彬 | Hits:

[VHDL-FPGA-Verilog] rs_dec_enc_latest.tar

Description: RS encoder decoder on vhdl
Platform: | Size: 92160 | Author: subhashini | Hits:

[VHDL-FPGA-Verilog] RSencFlash

Description: RS(255,239) encoder for NAND Flash controller
Platform: | Size: 95232 | Author: 彭洪 | Hits:

[ELanguage] rs(31-19)

Description: 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.
Platform: | Size: 376832 | Author: jianghong | Hits:

[VHDL-FPGA-Verilog] ug_rs-compiler

Description: altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
Platform: | Size: 413696 | Author: tangmin | Hits:

[VHDL-FPGA-Verilog] 82be270ea751

Description: RS（255，239）编码器的VHDL语言源代码，希望能对大家有一定帮助-the code of the encoder of rs（255,239），hope can help you
Platform: | Size: 4096 | Author: 周达 | Hits:

[ELanguage] rs(63-45)

Description: 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
Platform: | Size: 15360 | Author: wzz | Hits:

[VHDL-FPGA-Verilog] RS-encoder

Description: RSC encoder in VHDL. Hope it helpful.
Platform: | Size: 4096 | Author: thang | Hits:

CodeBus www.codebus.net