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[VHDL-FPGA-Verilog] clock

Description: EDA用maxplus2开发设计的简易数字钟，适合初学者，vhdL语言-EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
Platform: | Size: 392192 | Author: zzz | Hits:

[VHDL-FPGA-Verilog] four_bit-data-selector

Description: 四位的数据选择器，可在maxplus2上运行并仿真-Four of the data selection, which can be run on the maxplus2 and Simulation
Platform: | Size: 54272 | Author: 孙晟轩 | Hits:

[VHDL-FPGA-Verilog] APDLL

Description: 数字锁相环的FPGA设计与实现，用maxplus2实现的-DPLL FPGA design and implementation, with maxplus2 achieve
Platform: | Size: 1235968 | Author: yinuo | Hits:

[Windows Develop] clock

Description: 时钟，用maxplus2做的，可以重置时间，可以设置闹铃。-The clock, with maxplus2 do,it can reset the time and set the alarm.
Platform: | Size: 442368 | Author: zhang | Hits:

[Windows Develop] Tpinng_panngh

Description: 这是用AHDL语言开发的一个PCI采集系统的逻辑源码，其中的乒乓设计思思路新颖，有兴趣的朋友能参考一下！编译环境为maxplus2 可直接使用。 -AHDL language developed a PCI acquisition system logic source code, which the novel ping-pong the design Chaosisi Road, friends who are interested can refer to! Compilation environment for maxplus2 can be used directly.
Platform: | Size: 439296 | Author: 李 | Hits:

[Other] DT

Description: 基于maxplus2的心跳记录器设计，可以显示，回放，报警-failed to translate
Platform: | Size: 1142784 | Author: lmk | Hits:

[Other] taxi

Description: 基于maxplus2的出租车计价器设计有行走和停止两种计费状态-failed to translate
Platform: | Size: 58368 | Author: lmk | Hits:

[Other] clock

Description: 基于maxplus2的数字电子时钟设计，定点报时响铃-failed to translate
Platform: | Size: 986112 | Author: lmk | Hits:

[Other systems] Maxplus2_Tut_v3.0

Description: file related to maxplus2 software
Platform: | Size: 77824 | Author: minkalpatel | Hits:

[Windows Develop] Tpinng_panngh

Description: 这是用AHDL语言开发的一个PCI采集系统的逻辑源码，其中的乒乓设计思思路新颖，有兴趣的朋友能参考一下！编译环境为maxplus2 可直接使用。-AHDL language developed a PCI acquisition system logic source code, which the novel ping-pong the design Chaosisi Road, friends who are interested can refer to! Compilation environment for maxplus2 can be used directly.
Platform: | Size: 439296 | Author: oodpr | Hits:

[Applications] jinzhi

Description: 实现进制转换，可在MAXPLUS2上实现，适合初学者-To achieve binary conversion can be realized in MAXPLUS2 for beginners
Platform: | Size: 1024 | Author: lei419517 | Hits:

[VHDL-FPGA-Verilog] Maxplus2_74LS161

Description: 用Maxplus2制作的实现74LS161数字芯片功能，入门级工程。-Maxplus2 made with digital chips to achieve 74LS161 function, entry-level engineering.
Platform: | Size: 23552 | Author: 杰克 | Hits:
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