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Description: 大家好没办法还是那句话
我现在用maxplus2有高手跟我联系请上qq94229631 手机13788910703上海的我姓曹-everyone no way I reiterate I will maxplus2 with a master please contact me on the phone 13788910703 qq94229631 I Shanghai surnamed Cao
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Size: 6209 |
Author: 曹延安 |
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Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
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Size: 998 |
Author: 罗兵武 |
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Description: 用vhdl实现一个fir滤波器
设计要求：
1．最小阻带衰减-30db。
2．带内波动小于1db．
3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
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Size: 3072 |
Author: 达闻西 |
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Description: vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.
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Size: 65520 |
Author: 梦雨 |
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Description: 这是用AHDL语言编写的一个PCI采集系统的逻辑源码，其中的乒乓设计思路新颖，有兴趣的朋友可以参考一下！编译环境为maxplus2-This is AHDL prepared a PCI Acquisition System logical source, the Table Tennis novel design concept, interested friends can take a look! Build environment for maxplus2
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Size: 437186 |
Author: 王宣强 |
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Description: 基于maxplus2的八位加法器，已经通过仿真-maxplus2 based on the eight Adder, through simulation
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Size: 1060 |
Author: 海洋 |
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Description: 关于CPLD的文章 不错的! 可以给菜菜参考下-article on the CPLD good! Can either under reference
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Size: 17325007 |
Author: 许辉 |
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Description: 用maxplus2实现的一种通用逻辑模块，背景是一个基于dsp的嵌入式开发板，上面的逻辑模块全用cpld实现。此模块可以供以后的嵌入式开发作参考。-maxplus2 achieved using a common logic modules, background is a DSP-based embedded development board, the above logic modules throughout cpld achieve. This module can be embedded for the future development for reference.
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Size: 435845 |
Author: hanchong |
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Description: 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example, the simulation methods and timing diagrams, is a good example to learn VHDL.
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Size: 339949 |
Author: bkd |
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Description: maxplus2变得电子钟程序/// /////
-maxplus2 become electronic bell procedures
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Size: 683364 |
Author: xuemiao |
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Description: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
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Size: 309997 |
Author: 蔡庆重 |
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Description: 用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2
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Size: 114838 |
Author: 自然风 |
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Description: 基于FPGA的usb程序，采用VHDL语言编写。
开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.
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Size: 140480 |
Author: 李浩 |
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Description: 是一个用 maxplus2做的vhdl 很平常的课程小设计 -is a maxplus2 do with vhdl very common small design courses
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Size: 11906 |
Author: 李宁 |
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Description: 带左拐的交通灯设计与25进制的加法计数器，Maxplus2软件中的Verilog语言编写-Neunggok with the design of traffic lights at 229 with the addition of 25 counters, simulated software Verilog language
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Size: 1894 |
Author: hujianj |
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Description: MAXPLUS2 自己编写的VHDL
4位除法器-MAXPLUS2 prepare themselves VHDL four Divider
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Size: 129113 |
Author: 刘建 |
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Description: 异步发送电路是基于MAXPLUS2软件开发的一种实用电路,已经编译成功,可使用.-asynchronous circuit is based on the development of software MAXPLUS2 a practical circuit, has been successfully compiled, can be used.
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Size: 848 |
Author: jill |
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Description: 实现D触发器的基本功能,D触发器的功能是时钟信号为上升沿时检测输入信号并将其赋值给输出信号并维持到下一个上升沿(压缩包内为所有MAXPLUS2程序)
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Size: 11169 |
Author: 刘美 |
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Description: 译码器的逻辑功能是将已赋予特定含义的一组二进制输入代码的原意\"翻译\"出来,变成对应的输出高低电平信号.该程序为3-8译码器.基于VHDL,其开发环境是MAXPLUS2.
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Size: 4714 |
Author: weixiaoyu |
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Description: 用maxplus2设计的心率计，能实现心率的测量，并且能分辨出心跳是否正常-Maxplus2 design with heart rate meter, measuring heart rate can be achieved, and can distinguish between normal heartbeat
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Size: 1046528 |
Author: 谢普等 |
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