Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - maxplus2

Search list

[VHDL-FPGA-Verilog] 数字钟VHDL设计

Description: maxplus2开发基于EDA数字钟VHDL设计
Platform: | Size: 468777 | Author: ray494 | Hits:

[VHDL-FPGA-Verilog] VHDL_交通灯系统

Description: 用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2
Platform: | Size: 114688 | Author: 自然风 | Hits:

[VHDL-FPGA-Verilog] ad cvtor

Description: 开发环境：maxplus2 a/d convortor-development environment : maxplus2 a/d convortor
Platform: | Size: 2048 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] SCAN-vhdl

Description: maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program
Platform: | Size: 1024 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] ledtest

Description: 用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2-for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K
Platform: | Size: 126976 | Author: 闪核 | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[Other] HDL编码风格与编码指南大家看看啊

Description: 大家好没办法还是那句话 我现在用maxplus2有高手跟我联系请上qq94229631 手机13788910703上海的我姓曹-everyone no way I reiterate I will maxplus2 with a master please contact me on the phone 13788910703 qq94229631 I Shanghai surnamed Cao
Platform: | Size: 6144 | Author: 曹延安 | Hits:

[VHDL-FPGA-Verilog] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 1024 | Author: 罗兵武 | Hits:

[VHDL-FPGA-Verilog] FIRvhdl

Description: 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

[VHDL-FPGA-Verilog] wodevhdl

Description: vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.
Platform: | Size: 65536 | Author: 梦雨 | Hits:

[VHDL-FPGA-Verilog] ping_pang

Description: 这是用AHDL语言编写的一个PCI采集系统的逻辑源码，其中的乒乓设计思路新颖，有兴趣的朋友可以参考一下！编译环境为maxplus2-This is AHDL prepared a PCI Acquisition System logical source, the Table Tennis novel design concept, interested friends can take a look! Build environment for maxplus2
Platform: | Size: 437248 | Author: | Hits:

[Embeded-SCM Develop] CPLDNEW

Description: 用maxplus2实现的一种通用逻辑模块，背景是一个基于dsp的嵌入式开发板，上面的逻辑模块全用cpld实现。此模块可以供以后的嵌入式开发作参考。-maxplus2 achieved using a common logic modules, background is a DSP-based embedded development board, the above logic modules throughout cpld achieve. This module can be embedded for the future development for reference.
Platform: | Size: 435200 | Author: hanchong | Hits:

[VHDL-FPGA-Verilog] EDAchuzuchejijia

Description: 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example, the simulation methods and timing diagrams, is a good example to learn VHDL.
Platform: | Size: 339968 | Author: bkd | Hits:

[VHDL-FPGA-Verilog] vhdl_fifo

Description: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
Platform: | Size: 309248 | Author: 蔡庆重 | Hits:

[Compress-Decompress algrithms] usb(FPGA)

Description: 基于FPGA的usb程序，采用VHDL语言编写。 开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.
Platform: | Size: 140288 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] HXRJTD

Description: 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
Platform: | Size: 754688 | Author: 健 | Hits:

[Linux-Unix] JTD

Description: 带左拐的交通灯设计与25进制的加法计数器，Maxplus2软件中的Verilog语言编写-Neunggok with the design of traffic lights at 229 with the addition of 25 counters, simulated software Verilog language
Platform: | Size: 2048 | Author: | Hits:

[Software Engineering] maxplus2shizishizhong

Description: 数字电子钟的设计 （二十四小时六十分钟六十秒）-digital electronic clock design (24 hours 60 minutes 60 seconds)
Platform: | Size: 500736 | Author: yan | Hits:

[VHDL-FPGA-Verilog] VHDLchufaqi

Description: MAXPLUS2 自己编写的VHDL 4位除法器-MAXPLUS2 prepare themselves VHDL four Divider
Platform: | Size: 129024 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] txd5

Description: 异步发送电路是基于MAXPLUS2软件开发的一种实用电路,已经编译成功,可使用.-asynchronous circuit is based on the development of software MAXPLUS2 a practical circuit, has been successfully compiled, can be used.
Platform: | Size: 1024 | Author: jill | Hits:
« 1 2 3 45 6 7 »

CodeBus www.codebus.net