Search - maxplus

[VHDL-FPGA-Verilog] juzhenjianpan

Description: 矩阵健盘设计！用了MAXPLUS软件！矩阵健盘设计！用了MAXPLUS软件！-juzhenjianpan
Platform: | Size: 220160 | Author: sb | Hits:

[VHDL-FPGA-Verilog] EXP-EPM3128_3256

Description: cpld/fpga芯片exp-epm3128/3256的详细说明，适用于quartus以及maxplus软件-cpld/fpga chip exp-epm3128/3256 a detailed description of the software for quartus and maxplus
Platform: | Size: 971776 | Author: Yolanda | Hits:

[VHDL-FPGA-Verilog] jiaotongdengsheji

Description: 这是一个交通灯控制的VHDL程序，用于maxplus平台，适合于EDA设计-This is a traffic light control, VHDL program for maxplus platform, suitable for EDA Design
Platform: | Size: 145408 | Author: 小黄 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 通过MAXPLUS软件做时钟信号发生器，可通过外部的拨码开关进行清零和预置数-Software made by MAXPLUS clock signal generator is available through an external DIP switch and preset number of cleared
Platform: | Size: 1419264 | Author: 易木 | Hits:

[ELanguage] 5_758_2

Description: 这个文件是maxplus的lincese，全的！用lincsse setup 即可安装它-This file is maxplus the lincese, all of the! It can be installed with lincsse setup
Platform: | Size: 2048 | Author: 李进 | Hits:

[Windows Develop] miaobiao

Description: 计时器的最长计时时间为l小时, 为此需要一个6位的显示器, 显示的最长时间为 59分59.99秒。具有开始暂停功能的秒表-miaobiao
Platform: | Size: 1113088 | Author: chenshilin | Hits:

[VHDL-FPGA-Verilog] My_Clock

Description: 发个我的第一个VHDL代码，秒表。可暂停继续.清0。-My first one made a VHDL code, and a stopwatch. Continue to be suspended. Qing 0.
Platform: | Size: 585728 | Author: jemofh | Hits:

[Other] modle

Description: 计算机组成之模型机实验,有在maxplus上的源文件和课程设计报告-Composed of a computer model of machine experiments, there is the maxplus source files and programs on the design report
Platform: | Size: 4340736 | Author: 韩世广 | Hits:

[VHDL-FPGA-Verilog] cunchushiboqi

Description: 用vhdl编写数字存储示波器，通过调试，仿真环境是maxplus-Vhdl digital storage oscilloscope with the preparation, through debugging, simulation environment is maxplusII
Platform: | Size: 466944 | Author: luyuan | Hits:

[Communication] 3FSK.vhd

Description: 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation method to achieve 3FSK. The input of the system clock frequency respectively 2 hours, 4 minutes and 8 frequency-divider to have these three kinds of frequencies. Through the digital baseband signals received three pairs of binary-coded level value, and use them as three elected a switch to a different frequency values were selected, select a different signal, in order to achieve 3FSK modulation.
Platform: | Size: 4096 | Author: 雷月 | Hits:

[VHDL-FPGA-Verilog] soda_machine

Description: 自动售货机的功能，内容源代码，在MAXPLUS的执行文件都有-Vending machine' s functionality, content source code, the implementation of the file are in the MAXPLUS
Platform: | Size: 231424 | Author: 林晓 | Hits:

[Other] poc

Description: The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.-A parallel output controller
Platform: | Size: 356352 | Author: 冯裕深 | Hits:

[Other] counter

Description: maxplus 设计的 10位计数器-maxplus 10-bit counter
Platform: | Size: 61440 | Author: 乐天猫 | Hits:

[Other] 8eda

Description: 八位抢答器，在ＭＡＸＰＬＵＳ平台下动行。用VHDL编的八位抢答器，EDA课设的一个经典题目源程序-8 Responder, in MAXPLUS platform moving line. With a series of eight Responder VHDL, EDA courses located the source of a classical subject
Platform: | Size: 2425856 | Author: 周勇 | Hits:

[Software Engineering] DDS

Description: 使用maxplus设计的正弦余弦信号发生器，包含两个表格文件-Sin/cos signal generator
Platform: | Size: 5120 | Author: 朱艳萍 | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[Other Embeded program] CPUsourcecode

Description: 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
Platform: | Size: 93184 | Author: 李敏 | Hits:

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