Search - maxplus

[VHDL-FPGA-Verilog] 100Examples

Description: 该源码为用VHDL（硬件描述语言）编写的100个实例的源代码，是学习VHDL的绝好资源。软件环境为maxplus10.2及以上版本或Quartus2。-The source for the use of VHDL (Hardware Description Language) preparation of the 100 examples of the source code, is an excellent resource to learn VHDL. Software environment for maxplus10.2 and above or Quartus2.
Platform: | Size: 209920 | Author: gung66 | Hits:

[SCM] clock

Description: 在MAXPLUS II 平台上用ahdl 写的电子钟，-MAXPLUS II platform in ahdl write with electronic clock
Platform: | Size: 278528 | Author: 谭曼琼 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 来自某名牌大学电子实验室的eda指导教程，主要介绍了maxplus2，适合初学者-From a prestigious university guide EDA Electronic lab tutorials, mainly the introduction maxplus2, suitable for beginners
Platform: | Size: 484352 | Author: xiaoshuai | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，-EDA courses used by Max Plus2 software, produced a half-adder, there are image files, documents have waveform, it is recommended to see,
Platform: | Size: 31744 | Author: jimchen | Hits:

[Embeded-SCM Develop] Interleave

Description: 在Maxplus软件平台开发的，使用原理图开发的fpga的纠错编码和交织以及解纠错和解交织的源码文件-In Maxplus software platform developed using the schematic diagram of the FPGA development of error-correcting coding and intertwined, as well as forward error correction solutions reconciliation of source documents interwoven
Platform: | Size: 4150272 | Author: 熊浩 | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[Other] CPLDMAXplus

Description: CPLD数字电路设计——使用MAX+plusⅡ入门篇.rar 不能错过的书籍-CPLD digital circuit design- the use of MAX+ Plus Ⅱ entry papers. Rar can not miss books
Platform: | Size: 13341696 | Author: twinslizzy | Hits:

[Books] logicdesigforFPGA

Description: 高级FPGA教学实验指导书－逻辑设计部分.pdf QuatusII5.0 是Altera 公司的最新产品。MaxplusII 是一套非常成功的PLD 开发软件，虽然QuartusII 已经推出了4 年，并且Altera 宣布不再对MaxplusII 进行升级，但至今仍有非常多的工程师在使用MaxplusII。 Altera 在QuartusII 中允许将软件界面设置为 MaxplusII 风格，以吸引MaxplusII 的用户转向QuartusII。安装QuartusII 时，软件会自动询问，你准备使用何种界面：QuartusII 还是Maxplus-Senior FPGA experimental teaching guide book- part of logic design. PdfQuatusII5.0 are Altera
Platform: | Size: 1091584 | Author: 董军 | Hits:

[ELanguage] yunsuanqi

Description: maxplus下连接硬件实现74181运算器-Connect the hardware to achieve maxplus calculator 74181
Platform: | Size: 130048 | Author: wenyu | Hits:

[VHDL-FPGA-Verilog] FIR_VHDL

Description: FIR滤波器的VHDL代码,可以修改冲击函数的值-FIR filter VHDL code can modify the impact of the value function
Platform: | Size: 1024 | Author: 李扬 | Hits:

[VHDL-FPGA-Verilog] KEYBOARD

Description: vhdl语言编写的电子密码锁的键盘程序，本源码复制在word中，请黏贴到MAXPLUS等相应软件下运行-VHDL language electronic locks the keyboard program, the source copy of the word, please stick to the appropriate software, such as MAXPLUS run
Platform: | Size: 5120 | Author: 网天才 | Hits:

[VHDL-FPGA-Verilog] 38yima

Description: 本文为用vhdl语言编写的38译码器，为doc格式，请先复制到相应软件例如maxplus中再使用。-This article was prepared by using VHDL language decoder 38 for doc format, please copy to the appropriate software such as maxplus in the re-use.
Platform: | Size: 2048 | Author: 网天才 | Hits:

[VHDL-FPGA-Verilog] 2to10

Description: 本文为用vhdl语言编写的2进制到10进制转换的程序，为doc格式，使用前复制于maxplus等相应软件中使用。-This article was prepared by using VHDL language 2 hex to 10 hex conversion procedures for the doc format, the use of pre-replication in maxplus, such as the use of corresponding software.
Platform: | Size: 3072 | Author: 网天才 | Hits:

[Software Engineering] 07302529

Description: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Platform: | Size: 244736 | Author: 翁浩达 | Hits:

[Printing program] thelabreportofthePrinciplesofComputerComposition.r

Description: 计算机组成原理实验报告：包括运算器组成实验，存储器，微控制器等实验-Principles of Computer Organization Experimental report: composition of the experimental devices, including computing, memory, microcontroller and other experimental
Platform: | Size: 283648 | Author: 戚佳 | Hits:

[Algorithm] FIR3

Description: 3阶FIR，输入位宽12BIT ALTERA MAXPLUS II 及更高版本可打开-FIR
Platform: | Size: 98304 | Author: 项四平 | Hits:

[VHDL-FPGA-Verilog] miffile

Description: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Platform: | Size: 1024 | Author: 何亮 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.
Platform: | Size: 4490240 | Author: 灿烂六月 | Hits:

[Other] 2psk_final

Description: 2dpsk,maxplus软件,包含连接原理图\各个模块程序代码,可运行,管脚已经封装,可直接下载到FPGA芯片-2dpsk, maxplus software, including schematic connection \ each module code can be run has been pin package, can be directly downloaded to FPGA chip
Platform: | Size: 163840 | Author: menger | Hits:

[Other] MAXPlus_license11.0

Description: use for max+plus11.0,含license.dat-for max+plus11.0 ,include license.dat
Platform: | Size: 3072 | Author: kukulangma | Hits:

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