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[SourceCode] verilog全数字锁相环pll

Description: verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Platform: | Size: 383668 | Author: sakajj | Hits:

[VHDL-FPGA-Verilog] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19456 | Author: 刘仪 | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Platform: | Size: 384000 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] 255

Description: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Platform: | Size: 154624 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] LIP1251CORE_pll

Description: Digital PLL Verilog module
Platform: | Size: 76800 | Author: jc | Hits:

[VHDL-FPGA-Verilog] pll

Description: quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
Platform: | Size: 125952 | Author: 刘 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] pll

Description: verilog硬件描述语言实现数字锁相环功能仿真,-Digital phase-locked loop using verilog
Platform: | Size: 1024 | Author: huashuyang | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
Platform: | Size: 1024 | Author: louxy | Hits:

[VHDL-FPGA-Verilog] PLL_success

Description: 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
Platform: | Size: 7787520 | Author: www | Hits:

[VHDL-FPGA-Verilog] DPWM

Description: 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
Platform: | Size: 500736 | Author: lw1997 | Hits:

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