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[Software Engineering] DesignofanMP3PortablePlayerUsingaCoolRunnerCPLD.ra

Description: 描述了用CoolRunner CPLD实现mp3 player的一种方法，值得学习
Platform: | Size: 226031 | Author: 黄强暴 | Hits:

[Embeded-SCM Develop] cpld

Description: 本文详细分析了COOLRUNNER系列CPLD的结构,特点及功能,使用VHDL语言实现数字逻辑,实现了水下冲击波记录仪电路的数字电路部分.
Platform: | Size: 324349 | Author: 郅银周 | Hits:

[Other resource] Interface 8051 to Coolrunner CPLD(Xilinx App)

Description: Interface 8051 to Coolrunner CPLD(Xilinx App)
Platform: | Size: 22978 | Author: 高威 | Hits:

[SCM] Interface 8051 to Coolrunner CPLD(Xilinx App)

Description: Interface 8051 to Coolrunner CPLD(Xilinx App)
Platform: | Size: 22528 | Author: 高威 | Hits:

[Software Engineering] DesignofanMP3PortablePlayerUsingaCoolRunnerCPLD.ra

Description: 描述了用CoolRunner CPLD实现mp3 player的一种方法，值得学习-Describes the CoolRunner CPLD with mp3 player realize a method, it is worth learning
Platform: | Size: 225280 | Author: 黄强暴 | Hits:

[Embeded-SCM Develop] cpld

Description: 本文详细分析了COOLRUNNER系列CPLD的结构,特点及功能,使用VHDL语言实现数字逻辑,实现了水下冲击波记录仪电路的数字电路部分.-In this paper, a detailed analysis of the CoolRunner CPLD series structure, characteristics and functions, the use of VHDL language digital logic, the realization of the underwater shock wave logger s digital circuit part of the circuit.
Platform: | Size: 323584 | Author: | Hits:

[Communication-Mobile] APPILICATIONOFXILINXCPLD

Description: CPLD COOLRUNNER XILINX -CPLD COOLRUNNER XILINX
Platform: | Size: 215040 | Author: goodweiping | Hits:

[Other] uc_interface

Description: This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system. -This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system.
Platform: | Size: 4096 | Author: alex | Hits:

[Embeded-SCM Develop] VariPOD_src_0.2

Description: GUI for Amontec Chameleon POD clone with Xilinx Coolrunner inside.
Platform: | Size: 24576 | Author: Vaclav Peroutka | Hits:

[Industry research] cpld_applications_handbook_I

Description: Xilinx handbook for CPLD applications, featuring CoolRunner-II and XC9500XL CPLDs - Part I
Platform: | Size: 865280 | Author: sray | Hits:

[Software Engineering] pBlazIDE36

Description: There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as the PIC, 8051, AVR, 6502, 8080, and Z80 microcontrollers. The Xilinx PicoBlaze microcontroller is specifically designed and optimized for the Virtex and Spartan series of FPGAs and CoolRunner-II CPLDs.
Platform: | Size: 591872 | Author: biodun | Hits:

[VHDL-FPGA-Verilog] NANDInterface

Description: Xinlix CoolRunner-II cpld实现的nand FLASH接口-Xinlix CoolRunner-II cpld implementation nand FLASH Interface
Platform: | Size: 870400 | Author: 雷虎 | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: spi协议简介及简单的spi接口的描述和基于CoolRunner CPLD 的SPI设计结构-Introduction and simple protocol spi spi interface description of the SPI CoolRunner CPLD-based design structure
Platform: | Size: 82944 | Author: yangshisong | Hits:

[VHDL-FPGA-Verilog] I2C_control

Description: Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************************** ******************************************************************************************************************************************** File Contents ******************************************************************************************************************************************** This zip file contains the following folders: \doc -- Document for the CoolRunner I2C Controller. \exemplar -- Exemplar synthesis files. This design was synthesized using Exemplar and the resulting EDIF file imported into XPLA Professional V3.22 \vhdl_source -- Source VHDL files: i2c.vhd - top level file i2c_control.vhd - control function for the I2C master/slave shift.vhd - shift register uc_interface.vhd- uC interface f
Platform: | Size: 150528 | Author: leon | Hits:

[VHDL-FPGA-Verilog] I2C_vhdl

Description: IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the CoolRunner CPLD. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as Schmitt Triggers will be required to interface to the CPLD.
Platform: | Size: 849920 | Author: vijendra pal | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Platform: | Size: 10240 | Author: vijendra pal | Hits:

[VHDL-FPGA-Verilog] manchester_vhdl

Description: This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Platform: | Size: 11264 | Author: vijendra pal | Hits:

[VHDL-FPGA-Verilog] spi_cpld_vhdl

Description: The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of SPI Flash memories. Included in the source code spi_cpld.vhd is a list of other memories and their associated instructions for your convenience. -The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of SPI Flash memories. Included in the source code spi_cpld.vhd is a list of other memories and their associated instructions for your convenience.
Platform: | Size: 441344 | Author: vijendra pal | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device. -The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Platform: | Size: 5120 | Author: vijendra pal | Hits:

[VHDL-FPGA-Verilog] DDR-with-CoolRunner-II

Description: 详细讲解了CoolRunner II CPLD与DDR SDRAM的接口设计-Explained in detail about the design of the CoolRunner II CPLDs and DDR SDRAM interface
Platform: | Size: 368640 | Author: yanghengxu | Hits:
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