Description: The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
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File list (Check if you may need any files):
uart_verilog\rcvr.v
............\rcvr_tf.v
............\readme.txt
............\txmit.v
............\txmit_tf.v
............\uart.v
uart_verilog
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