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[VHDL-FPGA-Verilog] State.Machine

Description: State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
Platform: | Size: 123904 | Author: | Hits:

[VHDL-FPGA-Verilog] Verilog-statemachine

Description: 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
Platform: | Size: 183296 | Author: 张厂 | Hits:

[Other] statemachine11.2

Description: 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
Platform: | Size: 2048 | Author: 陶玉辉 | Hits:

[Other] 8.10

Description: 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
Platform: | Size: 18432 | Author: 陶玉辉 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[Other] how_to_write_state_machine

Description: 介绍写状态机的好资料，大家下载啊 基于VERILOG的-Write state machine introduce good information, everyone download ah Verilog based on the
Platform: | Size: 294912 | Author: 段小康 | Hits:

[Software Engineering] elevator

Description: 基于VHDL程序设计电梯的状态机.共六层的电梯有16个输入.其中包括5个上升,5个下降和六个电梯内的控制部分.-Program Design Based on VHDL elevator state machine. A total of 16 six-storey elevator input. Including five increased, five declined and six parts of the elevator control.
Platform: | Size: 333824 | Author: 范生德 | Hits:

[VHDL-FPGA-Verilog] 3-1

Description: 自动卖报机，5分一份，有1，2，5分类型的硬币。verilog状态机-Automatic selling newspaper machine, a 5 minutes, there are 1,2,5 classification type coins. Verilog state machine
Platform: | Size: 1024 | Author: 冯杰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] at24c02

Description: 基于FPGA的24C02驱动程序，使用有限状态机～结构完整，测试通过。-FPGA-based 24C02 driver, the use of finite state machine ~ structural integrity of the test.
Platform: | Size: 1156096 | Author: edjj | Hits:

[VHDL-FPGA-Verilog] USB_jtag

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Platform: | Size: 1571840 | Author: 霍飘摇 | Hits:

[VHDL-FPGA-Verilog] 4bit_buma_adder

Description: Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test bed, through the Modelsim, Synplify simulation.
Platform: | Size: 2048 | Author: wizard | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine

Description: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Platform: | Size: 121856 | Author: rex | Hits:

[VHDL-FPGA-Verilog] telephone

Description: 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
Platform: | Size: 1024 | Author: 邱波 | Hits:

[VHDL-FPGA-Verilog] state-machine-design

Description: 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog　learners
Platform: | Size: 189440 | Author: 王建伟 | Hits:

[VHDL-FPGA-Verilog] Verilog-state-machine

Description: 状态机采用 VerilogHDL 语言编码，建议分为三个 always 段，本文档就是详述其原因-VerilogHDL language code using the state machine, the proposed section is divided into three always
Platform: | Size: 616448 | Author: 老虎 | Hits:

[VHDL-FPGA-Verilog] verilog-state-machine

Description: 使用VerilogHDL语言的小教程。 用三段式方法编写状态机。 有清晰详细的注释。-A small tutorial teaching how to write the state machine using three-step method in VerilogHDL language. There are clear and detailed notes in the tutorial.
Platform: | Size: 335872 | Author: juzi | Hits:

[VHDL-FPGA-Verilog] state-machine

Description: 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word
Platform: | Size: 70656 | Author: csy | Hits:
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