4bit_buma_adder Verilog operation: the source code

Title: 4bit_buma_adder

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
duanwenyi880

Description: Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test bed, through the Modelsim, Synplify simulation.

Downloaders recently: [More information of uploader duanwenyi880]

To Search: Verilog state machine Verilog machine synplify cordic verilog

[ModelSim6c_SE_Cracker] - crack for ModelSim, a Verilog. VHDL and
[DDS51] - this program functions : DDS folder proc
[fpga-jpeg-verilog] - fpga-jpeg-verilog FPGA platform used in
[unsigned_4_adder] - Through the VHDL language realize the nu
[AnalyzingdesignswithModelsimQuartusII] - ModelSim
[VHDL] - This article describes the use of exampl
[code] - modelsim M counter 60 under the source f
[Flash] - Samsung' s flash programming Verilog
[synplify_ref_ug] - Synplify guide, there vhdl, verilog, sys

File list (Check if you may need any files):

4bit_buma_adder
...............\adder.v
...............\adderfms.v
...............\add_top.v

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net