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[Applications] manchester

Description: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Platform: | Size: 4131 | Author: 刘波 | Hits:

[Other resource] Manchester-AVR

Description: Manchester码解码算法的AVR单片机实现
Platform: | Size: 332054 | Author: 林永平 | Hits:

[Applications] manchester

Description: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Platform: | Size: 4096 | Author: 刘波 | Hits:

[Communication-Mobile] 曼彻斯特编解码Verilog代码

Description: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
Platform: | Size: 10240 | Author: 崔广辉 | Hits:

[Internet-Network] Mafffnchester

Description: 一个曼彻斯特编码解码器以及差分曼彻斯特编码解码程序，Vc＋＋6下编译通过-a Manchester encoding decoder difference Manchester encoding and decoding process, Vitamin C++ 6.0 compiler through
Platform: | Size: 229376 | Author: 杨圣湖 | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。-Based on FPGA/CPLD, using VHDL language codec Manchester realize. Manchester code also includes documentation.
Platform: | Size: 175104 | Author: 周水斌 | Hits:

[SCM] Manchester-AVR

Description: Manchester码解码算法的AVR单片机实现-Manchester code decoding algorithm of the AVR Microcontroller
Platform: | Size: 331776 | Author: 林永平 | Hits:

[File Format] Manchester

Description: “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
Platform: | Size: 1024 | Author: 冯小晶 | Hits:

[VHDL-FPGA-Verilog] manchester-code

Description: 曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0，低→ 高的跳变表示为1。每个码元中间都要发生跳变，接收端可将此变化提取出来作为同步信号，使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
Platform: | Size: 91136 | Author: 魏伟 | Hits:

[Mathimatics-Numerical algorithms] Manchester

Description: 16 位 二进制 随机数 生产 函数和Manchester编码-16-bit binary random number production function and Manchester encoding
Platform: | Size: 3072 | Author: achun | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
Platform: | Size: 40960 | Author: cst008 | Hits:

[matlab] Manchester

Description: 用matlab实现的曼彻斯特编码。50 占空比（可调）。绘制时域波形和频域功率谱密度。结果跟北邮的郭文斌的通信原理课件上的形状一模一样。-Manchester encoding with a matlab implementation. 50 duty cycle (adjustable). Draw time-domain waveform and frequency domain power spectral density. The results with the Beijing University of Posts and Telecommunications of the GUO of communication theory on the shape of the same courseware.
Platform: | Size: 2048 | Author: 李刚 | Hits:

[SCM] Manchester

Description: 使用C语言编写的曼彻斯特编码和解码功能函数-Written in C language with Manchester encoding and decoding functions
Platform: | Size: 1024 | Author: firebire | Hits:

[Other] manchester

Description: 该程序主要是完成曼彻斯特码的，编码，同步，加噪，译码，计算误码率等功能。-the program main contain manchester code, synchronization, add the gauss noise and so on
Platform: | Size: 155648 | Author: hmg | Hits:

[VHDL-FPGA-Verilog] manchester

Description: verilog 实现manchester编解码，最高速率5mhz-verilog manchester code to achieve the highest rate of 5mhz
Platform: | Size: 4096 | Author: 王红星 | Hits:

[SCM] manchester-coding

Description: 使用51单片机进行曼彻斯特编解码，编码程序中有同步头，结束位设置，解码有查找同步头，有效跳变检测等程序，内有proteus仿真原理图-With 51 single-chip codec to Manchester, there are sync, the end bit is set, decode sync with search, detection procedures are not effective, there proteus simulation schematic
Platform: | Size: 12288 | Author: 管俊波 | Hits:

[Other] Manchester-coding-

Description: 曼彻斯特编码与差分曼彻斯特编码详解，曼彻斯特编码（Manchester Encoding），也叫做相位编码(PE)是一个同步时钟编码技术，被物理层用来编码一个同步位流的时钟和数据。-Manchester coding with the difference in manchester. manchester code to labour code （ manchester encoding ）, also called phase encoding (pe) is a synchronization code, the technology is the physical layer is used to encode a synchronization of the clock and data.
Platform: | Size: 27648 | Author: wanwei | Hits:

[VHDL-FPGA-Verilog] manchester

Description: 源码包含三个模块，数据发送模块是读取FIFO中的数据后，将并行数据转换为串行，同时对串行数据进行曼彻斯特编码输出。数据接收模块是对接收的数据进行曼彻斯特解码。FIFO控制器模块将接收的串行数据转换为并行，并存储。 曼彻斯特解码部分本文采用了过采样技术，使用了一个8倍时钟进行采样。每一个数据周期采样8次，每四次采样确定一个状态，如果采样到三次及以上高电平则认为是高状态，否则认为是低状态。状态由高到底则是数据0，由低到高则是状态1。-Source consists of three modules, data transmission module is to read the FIFO data, the parallel data into serial, while the Manchester encoded serial data output. Data receiving module is receiving data from the Manchester decoder. FIFO controller module will receive the serial data into parallel, and storage. Manchester decoding part of the paper, the sampling technique, using a sampling clock 8 times. Each cycle of data sampling eight times, four times per sample to determine a state, if the sample into three or more is considered high-high state, otherwise considered a low state. State data from high in the end is 0, from low to high is the state 1.
Platform: | Size: 4096 | Author: 陈建 | Hits:

[Other] nrz and manchester

Description: model simulink of manchester and nrz modulation
Platform: | Size: 9216 | Author: faycel | Hits:

[Communication-Mobile] manchester

Description: 关于曼彻斯特码和差分曼切斯特码在matlab中的程序实现，可运行(THE MANCHESTER OF MATLAB)
Platform: | Size: 61440 | Author: 汤姆不苏 | Hits:
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