Search - HDLC - CodeBus

[Other] HDLC

Description:
Platform: | Size: 4096 | Author: 东方飘云 | Hits:

[Internet-Network] HDLC_Viewer

Description: HDLC 的测试程序,方便串口开发中的数据验证-HDLC testing procedures to facilitate the development of data validation serial
Platform: | Size: 56320 | Author: 东方 | Hits:

Description: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Platform: | Size: 11264 | Author: 卓福洲 | Hits:

[Internet-Network] open_hdlc_src

Description: OSHDLC is the software implementation of High Level Data Link Control (HDLC) standard. It is an optimized C-code. It may be used on lots of platforms easily. -OSHDLC is the software implementation of High Level Data Link Control (HDLC) standard. It is an optimized C-code. It may be used on lots of platforms easily.
Platform: | Size: 37888 | Author: tangzhenxing | Hits:

[VHDL-FPGA-Verilog] hdlc_latest[1]

Description: HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
Platform: | Size: 573440 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] dddddddHDLC

Description: FPGA的入门级资料讲的很好不错 hdlc的实现-fpga
Platform: | Size: 2253824 | Author: wangyang | Hits:

[VHDL-FPGA-Verilog] hdlc_rs

Description: 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual process
Platform: | Size: 6144 | Author: 周宽裕 | Hits:

[VC/MFC] EX_Checksum

Description: check sum of hdlc ok ok
Platform: | Size: 1024 | Author: Quang | Hits:

[VHDL-FPGA-Verilog] hdlc_decode

Description: 基于Verilog的HDLC解码器。其中时钟的提取采用数字锁相环-The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
Platform: | Size: 2716672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] hdlc_encode

Description: 基于Verilog的HDLC解码器。输出外接485进行差分输出。-HDLC-based Verilog decoder. Output of an external differential output 485.
Platform: | Size: 4623360 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] hdlc_latest

Description: hdlctest负责HDLC编码,wishone接口，包括插0，FIFO-hdlctest responsible for the HDLC encoding, wishone interface, including the inserted 0, FIFO, etc.
Platform: | Size: 460800 | Author: wgy596 | Hits:

[Program doc] HDLC---A-Technical-Overview

Description: HDLC Protocol Overview
Platform: | Size: 33792 | Author: morteza | Hits:

[Program doc] HDLC-Protocol-Description

Description: HDLC Protocol-HDLC Protocol
Platform: | Size: 23552 | Author: morteza | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC code in vhdl working code
Platform: | Size: 39936 | Author: hr | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: hdlc ip core in communication
Platform: | Size: 808960 | Author: Ramanathan.SP. | Hits:

[Other] HDLC-PPP1

Description: 通过本实验，读者可以掌握如下技能： ① 串行链路上的封装概念； ② HDLC封装； ③ PPP封装。 -Through this experiment, the reader can grasp the following skills: ① serial link encapsulation concept ② HDLC encapsulation ③ PPP encapsulation.
Platform: | Size: 15360 | Author: 李腾 | Hits:

[ELanguage] hdlc

Description: hdlc decoder and AX.25 packet dump
Platform: | Size: 5120 | Author: mmktech | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other] HDLC

[Internet-Network] HDLC_Viewer

[Com Port] HDLC_VHDL

[Internet-Network] open_hdlc_src

[VHDL-FPGA-Verilog] hdlc_latest[1]

[VHDL-FPGA-Verilog] dddddddHDLC

[VHDL-FPGA-Verilog] hdlc_rs

[VC/MFC] EX_Checksum

[VHDL-FPGA-Verilog] hdlc_decode

[VHDL-FPGA-Verilog] hdlc_encode

[VHDL-FPGA-Verilog] hdlc_latest

[Program doc] HDLC---A-Technical-Overview

[Program doc] HDLC-Protocol-Description

[VHDL-FPGA-Verilog] hdlc

[VHDL-FPGA-Verilog] hdlc

[Other] HDLC-PPP1

[ELanguage] hdlc

[VHDL-FPGA-Verilog] hdlc

[Windows Develop] HDLC

[VHDL-FPGA-Verilog] hdlc

CodeBus www.codebus.net