Description: hdlctest responsible for the HDLC encoding, wishone interface, including the inserted 0, FIFO, etc.
To Search:
- [hdlc] - HDLC controller base on FPGA
- [HDLC] - written in verilog HDL HDLC protocol IP
- [sobel] - Verilog，Sobel Operator
File list (Check if you may need any files):
hdlc_latest\hdlc\tags\init\CODE\LIBS\hdlc_components_pkg.vhd
...........\....\....\....\....\RX\CORE\flag_detect.vhd
...........\....\....\....\....\..\....\RxChannel.vhd
...........\....\....\....\....\..\....\Rxcont.vhd
...........\....\....\....\....\..\....\Zero_detect.vhd
...........\....\....\....\....\..\SCRIPTS\WAVE.DO
...........\....\....\....\....\..\TB\Rx_tb.vhd
...........\....\....\....\DOCS\hdlc_features.txt
...........\....\....\....\....\hdlc_project.tex
...........\....\....\....\....\HDLC_top.dia
...........\....\....\....\ETC\HDLC_top.jpg
...........\....\.runk\CODE\LIBS\hdlc_components_pkg.vhd
...........\....\.....\....\....\PCK_CRC16_D8.vhd
...........\....\.....\....\MEM_PKG.VHD
...........\....\.....\....\RX\CORE\flag_detect.vhd
...........\....\.....\....\..\....\RxChannel.vhd
...........\....\.....\....\..\....\Rxcont.vhd
...........\....\.....\....\..\....\Zero_detect.vhd
...........\....\.....\....\..\SCRIPTS\WAVE.DO
...........\....\.....\....\..\TB\Rx_tb.vhd
...........\....\.....\....\SPMEM.VHD
...........\....\.....\....\tools_pkg.vhd
...........\....\.....\....\TOP\core\hdlc.vhd
...........\....\.....\....\...\....\RxBuff.vhd
...........\....\.....\....\...\....\RxFCS.vhd
...........\....\.....\....\...\....\RxSync.vhd
...........\....\.....\....\...\....\TxBuff.vhd
...........\....\.....\....\...\....\TxFCS.vhd
...........\....\.....\....\...\....\TxSync.vhd
...........\....\.....\....\...\....\WB_IF.vhd
...........\....\.....\....\...\scripts\model\build_hdlc_top.do
...........\....\.....\....\...\.......\.....\build_TxFCS_Buff.do
...........\....\.....\....\...\.......\.....\wave.do
...........\....\.....\....\...\.......\nc-sim\build_hdlc_top.csh
...........\....\.....\....\...\.......\......\build_RxFCS_Buff.csh
...........\....\.....\....\...\.......\......\build_TxFCS_Buff.csh
...........\....\.....\....\...\.......\......\cds.lib
...........\....\.....\....\...\.......\......\hdl.var
...........\....\.....\....\...\tb\hdlc_tb.vhd
...........\....\.....\....\...\..\RxTop_tb.vhd
...........\....\.....\....\...\..\TxTop_tb.vhd
...........\....\.....\....\.X\core\flag_ins.vhd
...........\....\.....\....\..\....\TxChannel.vhd
...........\....\.....\....\..\....\TXcont.vhd
...........\....\.....\....\..\....\zero_ins.vhd
...........\....\.....\....\..\scripts\wave.do
...........\....\.....\....\..\tb\tx_tb.vhd
...........\....\.....\DOCS\hdlc_features.txt
...........\....\.....\....\hdlc_project.pdf
...........\....\.....\....\hdlc_project.tex
...........\....\.....\....\HDLC_top.dia
...........\....\.....\ETC\HDLC_top.jpg
...........\....\web_uploads\HDLC_cont.jpg
...........\....\...........\HDLC_cont.ps
...........\....\...........\hdlc_fifo.jpg
...........\....\...........\hdlc_fifo.ps
...........\....\...........\hdlc_project.html
...........\....\...........\hdlc_project.ps
...........\....\...........\HDLC_top.jpg
...........\....\...........\HDLC_top.ps
...........\....\...........\index.shtml
...........\....\...........\wishlogo.ps
...........\....\tags\init\CODE\RX\CORE
...........\....\....\....\....\..\SCRIPTS
...........\....\....\....\....\..\TB
...........\....\.runk\CODE\TOP\scripts\model
...........\....\.....\....\...\.......\nc-sim
...........\....\.ags\init\CODE\LIBS
...........\....\....\....\....\RX
...........\....\.runk\CODE\RX\CORE
...........\....\.....\....\..\SCRIPTS
...........\....\.....\....\..\TB
...........\....\.....\....\TOP\core
...........\....\.....\....\...\scripts
...........\....\.....\....\...\tb
...........\....\.....\....\.X\core
...........\....\.....\....\..\scripts
...........\....\.....\....\..\tb
...........\....\.ags\init\CODE
...........\....\....\....\DOCS
...........\....\....\....\ETC
...........\....\.runk\CODE\LIBS
...........\....\.....\....\RX
...........\....\.....\....\TOP
...........\....\.....\....\TX
...........\....\.ags\init
...........\....\.runk\CODE
...........\....\.....\DOCS
...........\....\.....\ETC
...........\....\branches
...........\....\tags
...........\....\trunk
...........\....\web_uploads
...........\hdlc
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