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[VHDL-FPGA-Verilog] fifo

Description: fpga中fifo的基本原理介绍了fifo的基本原理以及对fifo实现方法的阐述。-The basic principle in fpga fifo fifo introduced the basic principles and methods of implementation described fifo.
Platform: | Size: 527360 | Author: 何敬武 | Hits:

[USB develop] FX2-Slave-FIFO

Description: 最常用的USB数据采集系统 CY7C68013 SLAVE FIFO 模式 不需要修改，已验证过-The most common USB data acquisition system CY7C68013 SLAVE FIFO mode does not change, has been verified
Platform: | Size: 66560 | Author: 高亮 | Hits:

[VHDL-FPGA-Verilog] Verilog_CY7C68013-SLAVE-FIFO

Description: 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
Platform: | Size: 667648 | Author: 高亮 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Platform: | Size: 432128 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] Asynchronous-FIFO-design

Description: 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss probability is not zero. How to design a high reliability, high speed asynchronous FIFO is a difficulty, this code introduced a kind of solution.
Platform: | Size: 3072 | Author: 王国庆 | Hits:

[VHDL-FPGA-Verilog] fifo-VerilogHDL

Description: 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
Platform: | Size: 5120 | Author: 王体奎 | Hits:

[SCM] cy7c68013-Slave-FIFO

Description: cy7c68013 slave fifo fw
Platform: | Size: 17408 | Author: lgw21 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: verilog实现fifo，ise中仿真，chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
Platform: | Size: 4930560 | Author: xiangxj | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于fpga的fifo的设计与实现，好东西，希望大家喜欢-Fpga-based design and implementation of fifo, good things, hope you like
Platform: | Size: 157696 | Author: 杜 | Hits:

[OS Develop] FIFO-LRU-OPT-Clock

Description: 页面置换算法，FIFO，LRU，OPT，NUR。-Page replacement algorithm
Platform: | Size: 15360 | Author: soong | Hits:

[VHDL-FPGA-Verilog] fifo

Description: Verilog HDL实现复杂逻辑设计FIFO-Verilog HDL to achieve FIFO
Platform: | Size: 1024 | Author: 开山刀 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 详细介绍了fifo深度计算的方法，fifo深度的计算是面试中常被问到的问题！-Fifo depth details of the method of calculation, fifo depth calculation is frequently asked interview questions!
Platform: | Size: 6144 | Author: haohao | Hits:

[VHDL-FPGA-Verilog] quartusII-FIFO

Description: 教你如何用QuartusII软件设计FIFO-us QuartusII design FIFO
Platform: | Size: 2050048 | Author: 李璞玉 | Hits:

[Other] FIFO Design

Description: 异步fifo设计经典文章，可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
Platform: | Size: 124928 | Author: xinx13 | Hits:

[SCM] fifo

Description: 一个简单的FIFO实现，基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)
Platform: | Size: 1024 | Author: 与众漫步 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)
Platform: | Size: 1024 | Author: chenxuan123456 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
Platform: | Size: 2048 | Author: ttian | Hits:

[VHDL-FPGA-Verilog] Synchronous FIFO

Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Platform: | Size: 264192 | Author: 渔火 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO的功能众所周知，非常好的处理时序问题。(The functions of FIFO are known to be very good at dealing with timing problems.)
Platform: | Size: 1024 | Author: FollowSky | Hits:

[Other] SCI.fifo

Description: DSP2812SCI通信程序，采用 fifo模式(DSP2812SCI communication procedures, using fifo mode)
Platform: | Size: 88064 | Author: 是雕 | Hits:
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