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[VHDL-FPGA-Verilog] Asynchronous-FIFO

Description: Asynchronous FIFO Implementation in VHDL
Platform: | Size: 65536 | Author: Mufossa | Hits:

[OS Develop] FIFO

Description: c语言编写的FIFO页面淘汰算法，对页面访问序列进行处理，显示出换页的过程，并求出缺页率。-c language FIFO page replacement algorithm for page access sequence is processed, showing the paging process and seek vacancy rates page.
Platform: | Size: 1024 | Author: 较傻的瓜 | Hits:

[OS program] fifo

Description: windows FIFO(fifo)实现，已经在win32平台验证，需要用户自己实现互斥锁；
Platform: | Size: 1024 | Author: money_001 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的8位fifo 1s发送10个8位数据，采用的是verilog 编程语言，入门，方便各位学习-Eight fifo based on FPGA 1 s sent 10 8 bits of data, USES is verilog programming language, introduction, convenient for you to learn
Platform: | Size: 5357568 | Author: 西大楼107 | Hits:

[Internet-Network] FIFO

Description: sample verilog FIFO design
Platform: | Size: 2048 | Author: luttie | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
Platform: | Size: 10240 | Author: WPI | Hits:

[Other] FIFO

Description: 这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.
Platform: | Size: 1210368 | Author: 李刚 | Hits:

[Windows Develop] FIFO-page-replacement-algorithm

Description: ×FIFO页面置换算法例如：进程P有5个页，进程访问页的顺序为：1，2，3，4，1，2，5，1，2，3，4，5；如果在内存中分配给该进程3个页面，则缺页情况 -FIFO page replacement algorithm such as: process P has five pages, the process to access pages in the order: 1,2,3,4,1,2,5,1,2,3,4,5 If the memory allocation to the process three pages, missing page case
Platform: | Size: 8192 | Author: 李亮 | Hits:

[SCM] fifo

Description: 单片机FIFO的设置以及中断和读写程序的源码-FIFO chip set and interrupt source and literacy programs
Platform: | Size: 1024 | Author: 张明艳 | Hits:

[OS Develop] FIFO

Description: 模拟请求页式存储管理中硬件的地址转换和缺页中断，并用先进先出调度算法（FIFO）处理缺页中断。-Simulation request page storage management hardware address translation and page fault, and use FIFO scheduling algorithm (FIFO) handling page fault.
Platform: | Size: 1133568 | Author: Toby | Hits:

[OS program] FIFO-process-scheduling

Description: 用C语言实现进程调度算法FIFO的模拟过程-C language simulation process scheduling algorithm FIFO process
Platform: | Size: 195584 | Author: wen | Hits:

[Data structs] FIFO-Replacement-algorithm

Description: FIFO 置换算法操作系统大作业FIFO源代码-FIFO Replacement algorithm
Platform: | Size: 1024 | Author: | Hits:

[SCM] fifo

Description: 一个很好用的fifo，已经在工程中应用过-A good use of fifo, had been applied in the project
Platform: | Size: 2048 | Author: liu | Hits:

[Other] fifo

Description: 同步FIFO设计一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow flag. Please use the code can be integrated programming style.
Platform: | Size: 1024 | Author: 王谦 | Hits:

[assembly language] fifo

Description: 同步fifo vhdl语言 16乘以8 能够进行仿真- 16 synchronous fifo vhdl language can be simulated by 8
Platform: | Size: 18432 | Author: 浅桑 | Hits:

[JSP/Java] FIFO

Description: FIFO TOURNIQUET RMA DMA ALgorithme in java BY CHACHOU MOHAMMED Morocco raaaaaaaa9-FIFO TOURNIQUET RMA DMA ALgorithme in java BY CHACHOU MOHAMMED Morocco raaaaaaaa9
Platform: | Size: 55296 | Author: mohammed | Hits:

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[VHDL-FPGA-Verilog] Asynchronous-FIFO

[OS Develop] FIFO

[OS program] fifo

[VHDL-FPGA-Verilog] FIFO

[Internet-Network] FIFO

[VHDL-FPGA-Verilog] FIFO

[Other] FIFO

[Windows Develop] FIFO-page-replacement-algorithm

[SCM] fifo

[OS Develop] FIFO

[OS program] FIFO-process-scheduling

[Data structs] FIFO-Replacement-algorithm

[SCM] fifo

[Other] fifo

[assembly language] fifo

[JSP/Java] FIFO

[SCM] UART-fifo-memcpy

[Other Embeded program] fifo

[Software Engineering] FIFO

[VHDL-FPGA-Verilog] fifo

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