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[VHDL-FPGA-Verilog] Traffic

Description: 使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.
Platform: | Size: 263168 | Author: 徐朝凯 | Hits:

[Other] LCD

Description: ALTERA上DE2平台，使用LCD模块，在LCD上显示字母字符。与已有程序相比，程序更加优化，代码更少。-ALTERA on DE2 platform, the use of LCD modules, LCD display in alphabetic characters. Compared with the existing procedures, procedures more optimized, less code.
Platform: | Size: 505856 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog] Time

Description: ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
Platform: | Size: 609280 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog] main

Description: altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success
Platform: | Size: 1024 | Author: 娟娟 | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

Description: 用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
Platform: | Size: 1600512 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration
Platform: | Size: 140288 | Author: Morgan | Hits:

[Embeded-SCM Develop] DE2_USB_API

Description: 用于AlRERA 公司DE2开发板上的USB 调试的实例-AlRERA company for the DE2 development board USB debug example
Platform: | Size: 1371136 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] DE2_CCD_CV

Description: altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver
Platform: | Size: 12056576 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_CCD

Description: 在altera DE2 的开发板上采集图像，到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.
Platform: | Size: 3439616 | Author: alison | Hits:

[SCM] DE2_70_User_manual_v101

Description: Altera DE2-70开发板的使用手册-Altera DE2-70 development board manual
Platform: | Size: 3685376 | Author: 桑圣锋 | Hits:

[VHDL-FPGA-Verilog] DE2_with_VGA_LCM

Description: altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
Platform: | Size: 2924544 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] Binary_VGA_Controller

Description: de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development
Platform: | Size: 79872 | Author: 陈斌 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: DE2开发板提供的四端口SDRAM驱动，用户不需要对SDRAM直接操作，把SDRAM对用户透明化-DE2 development board provides four-port SDRAM drive, users do not need to direct the operation of the SDRAM, the SDRAM transparent to users
Platform: | Size: 15360 | Author: 旺仔 | Hits:

[2D Graphic] DE2_CCD_binary

Description: verilog DE2 binary image (form CCD to VGA) output
Platform: | Size: 4235264 | Author: eknngx | Hits:

[VHDL-FPGA-Verilog] DE2_VGA3

Description: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Platform: | Size: 1275904 | Author: Donghua Gu | Hits:

[Graph program] vga

Description: 基于DE2板子的，VGA 图像显示，采用verilog语言-Based on the DE2 board, VGA image display, using Verilog language
Platform: | Size: 1024 | Author: 张梦 | Hits:

[Picture Viewer] DE2_CCD

Description: CCD的驱动程序，用于DE2板，可显示出摄像头采集的图像数据。-CCD driver for the DE2 board, show the camera s image data collection.
Platform: | Size: 1349632 | Author: churan | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_LITE_SRAM

Description: DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Platform: | Size: 1573888 | Author: 张曦 | Hits:

[VHDL-FPGA-Verilog] VHDL_VGA_Controller

Description: 基于DE2板子的，采用VHDL硬件描述语言实现图形的控制-Based on the DE2 board, and the use of VHDL hardware description language to achieve control of graphics
Platform: | Size: 79872 | Author: rain | Hits:

[VHDL-FPGA-Verilog] HardwareUDP

Description: Hardware UDP, implementation of UDP based on Altera DE2 using Verilog
Platform: | Size: 80896 | Author: Francis Wu | Hits:
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