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[assembly language] cpld DL : 0: 一个好用的整数分频电路保证你喜欢能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Date : 2008-10-13 Size : 915byte User : 王多奎
[assembly language] cpld DL : 0: 一个好用的整数分频电路保证你喜欢能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Date : 2025-12-19 Size : 1kb User : 王多奎
[assembly language] liushuideng DL : 0: 用verilog实现流水灯，适合cpld平台, 已经仿真成功的-Lights to achieve water use verilog for cpld platform has been successful simulation
Date : 2025-12-19 Size : 12kb User : liuxing
[assembly language] sram216 DL : 0: SRAM IS61LVC12824,读写控制程序，用CPLD 95216设计-SRAM IS61LVC12824, read and write control procedures, with the design of CPLD 95216
Date : 2025-12-19 Size : 1kb User : watson
[assembly language] AD_DA DL : 0: dsp2407+cpld的实验版源程序中的ad_da输入转换源程序，其中引出的是16通道中的0和8通道。-dsp2407+ cpld experimental version of the source of ad_da input conversion source, which leads the 16-channel and 8 channel 0.
Date : 2025-12-19 Size : 67kb User : leafageye
[assembly language] UART_RS232(verilog) DL : 0: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Date : 2025-12-19 Size : 586kb User : 饕餮小宇
[assembly language] UART_RS232(VHDL) DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Date : 2025-12-19 Size : 593kb User : 饕餮小宇
[assembly language] 9536 DL : 0: Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
Date : 2025-12-19 Size : 1kb User : Arao
[assembly language] AVR DL : 0: java单片机与CPLD综合应用技术电子元器件识别与检测经典入门教程-java integrated application of MCU and CPLD technology electronic components identification and detection of classic introductory tutorial
Date : 2025-12-19 Size : 246kb User : 罗毅
[assembly language] SPI-Core_nguyen DL : 0: SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE.STD_LOGIC_1164 IEEE.NUMERIC_STD work.general_signal_processing_pkg (included) Testbench for simulation included. Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
Date : 2025-12-19 Size : 17kb User : AgentNguyex
[assembly language] doGetFile DL : 0: 电气与电子工程专业，用于控制电机自动运行的CPLD程序代码-design for lift control
Date : 2025-12-19 Size : 3kb User : he yang
[assembly language] CAN-IP-Core DL : 0: CAN IP Core can硬件的IP核，用于cpld和fpga编程can接口-CAN IP Core
Date : 2025-12-19 Size : 117kb User : liucl