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[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Date : 2026-01-11 Size : 112kb User :
[VHDL-FPGA-Verilog] fip DL : 0: 通过PC104访问内存地址，内存需要进行地址选择，需要通过CPLD做地址逻辑变换。这个就是完成这个功能。实现简单。-Access through the PC104 memory address, memory address the need for choice, need to do address CPLD logic transformation. This is the completion of this function. Simple.
Date : 2026-01-11 Size : 662kb User : 周胜
[VHDL-FPGA-Verilog] uriscram DL : 0: RAM存储器：设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain. -RAM memory: Set 16 8 memory cell. If read = 1 is dataout
Date : 2026-01-11 Size : 1kb User : 良芯
[VHDL-FPGA-Verilog] sjcj DL : 0: 通过ADC0809对模拟信号进行采样，然后将转换好的8位数据迅速转存到FPGA内部存储器中，同时增加一个锯齿波发生电路，扫描时钟与地址发生时钟一致。由此完成一个示波器功能！-Through ADC0809 carried out on the analog signal sampling, and then a good 8-bit data conversion转存到rapid internal FPGA memory, at the same time increase the occurrence of a sawtooth circuit, scan clock and address clock line. Thus completed a oscilloscope function!
Date : 2026-01-11 Size : 695kb User : 江俊
[VHDL-FPGA-Verilog] VHDL-ROM4 DL : 0: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Date : 2026-01-11 Size : 96kb User : 宫逢源
[VHDL-FPGA-Verilog] ram DL : 0: 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Date : 2026-01-11 Size : 2kb User : 齐磊
[VHDL-FPGA-Verilog] cam_test DL : 0: 一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog-CAM a verified source (CAM = Content Address Memory). Language for Verilog
Date : 2026-01-11 Size : 30kb User : 天策
[VHDL-FPGA-Verilog] led_control DL : 0: 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0.
Date : 2026-01-11 Size : 1.15mb User : yangxiao
[VHDL-FPGA-Verilog] module DL : 0: 深入的理解总线的概念和特性，掌握总线的传输控制特点，熟悉计算机的数据通路概念和原理，了解其构建方法以及数据和地址是怎样在通路上传输的，将运算器模块与存储器模块连接起来，了解运算器和存储器是如何协调工作的。-Understanding of the concept and characteristics of the bus master the bus transfer control features, familiar with computer data access concepts and principles to understand the way it was built and how the data and address is transmitted in the channel, the computing module and memory modules connected understand the computing device, and memory is how to coordinate work.
Date : 2026-01-11 Size : 531kb User : 623902748
[VHDL-FPGA-Verilog] memtest DL : 0: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Date : 2026-01-11 Size : 218kb User : 平凡
[VHDL-FPGA-Verilog] compare DL : 0: 简单的原理性ROM 存储了地址的反码可以用LED显示-Simple principle of ROM code memory of the address counter with LED display can be
Date : 2026-01-11 Size : 2kb User : 梁天尺
[VHDL-FPGA-Verilog] zxcpu DL : 0: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Date : 2026-01-11 Size : 1.03mb User : zhaoshu
[VHDL-FPGA-Verilog] MicroController DL : 0: 了解EDA扩展板功能,利用实验系统伟福COP2000，自行设计微程序控制器和指令系统，能够实现数据传送，进行加、减运算和无条件转移，具有累加器寻址、寄存器寻址、寄存器间接寻址、存储器直接寻址、立即数寻址等五种寻址方式，并实现EDA控制。-Learn EDA expansion board function, use of experimental DW COP2000, self-designed micro-program controller and instruction, can achieve data transfer, and to add, subtract and unconditional transfer, with the accumulator addressing, register addressing, register indirectThe five addressing modes of address, direct memory addressing, immediate addressing, and to achieve EDA control.
Date : 2026-01-11 Size : 329kb User : 东方不败
[VHDL-FPGA-Verilog] zhegnxianbo DL : 0: 首先把正弦信号的数据写入存储器，通过控制程序给出的地址访问ROM存储器，不同的地址给出不同的数据从而将正弦信号读出来-First turn on the sine signal data writing memory, through the control program of the address given access ROM memory, different address given different data and the sine signal read out
Date : 2026-01-11 Size : 2kb User : 毕LONG
[VHDL-FPGA-Verilog] DDS-frequency-synthesizer DL : 0: 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Starting from the design requirements, this paper presents the detailed design of the DDS process, including the various modules of the design ideas, schematics, Verilog language code. The general idea of frequency control word and phase control word to control the address of the ROM memory table of the sine function and the corresponding get its amplitude value, and ultimately achieve the purpose of waveform output needs.
Date : 2026-01-11 Size : 795kb User : 任健铭
[VHDL-FPGA-Verilog] FIFO DL : 2: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单，但缺点就是只能顺序写入数据，顺序的读出数据，其数据地址由内部读写指针自动加1完成，不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址-FIFO is the abbreviation of the English First In First Out, a FIFO data buffer, the difference between ordinary memory is no external read and write address lines, so very simple to use, but the drawback is that the only order to write data sequential read data, the data address by the internal read and write pointer to automatically add one to complete, not like ordinary memory, as can be determined by the address lines to read or write to a specified address
Date : 2026-01-11 Size : 343kb User : 李海军
[VHDL-FPGA-Verilog] RISC-CPU DL : 1: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Date : 2026-01-11 Size : 3mb User : vice
[VHDL-FPGA-Verilog] DE2_70_NIOS_10_flash DL : 0: 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.
Date : 2026-01-11 Size : 1.55mb User : boyzone
[VHDL-FPGA-Verilog] memory DL : 0: Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd- Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd
Date : 2026-01-11 Size : 1kb User : mohamed
[VHDL-FPGA-Verilog] FINAL_CODE_CAM DL : 0: this is a VHDL code for content address memory
Date : 2026-01-11 Size : 173kb User : divya

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