First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.

DE2_70_NIOS_10_flash
....................\.sopc_builder
....................\.............\install.ptf
....................\.............\install2.ptf
....................\.............\preferences.xml
....................\AUDIO.v
....................\DE2_70.qpf
....................\DE2_70.qsf
....................\DE2_70.qws
....................\DE2_70_SOPC_sim
....................\...............\atail-f.pl
....................\...............\contents_file_warning.txt
....................\...............\dummy_file
....................\...............\jtag_uart_input_mutex.dat
....................\...............\jtag_uart_input_stream.dat
....................\...............\jtag_uart_output_stream.dat
....................\...............\uart_input_data_mutex.dat
....................\...............\uart_input_data_stream.dat
....................\...............\uart_log_module.txt
....................\DM9000A.v
....................\IP
....................\..\TERASIC_AUDIO
....................\..\.............\hdl
....................\..\.............\...\AUDIO_ADC.v
....................\..\.............\...\AUDIO_DAC.v
....................\..\.............\...\AUDIO_IF.v
....................\..\.............\...\AUDIO_IF.v.bak
....................\..\.............\...\AUDIO_IF_hw.tcl
....................\..\.............\...\audio_fifo.v
....................\..\.............\...\audio_fifo_wave0.jpg
....................\..\.............\...\audio_fifo_wave1.jpg
....................\..\.............\...\audio_fifo_waveforms.html
....................\..\.............\software
....................\..\.............\........\AUDIO.c
....................\..\.............\........\AUDIO.h
....................\..\.............\........\AUDIO_REG.h
....................\..\TERASIC_Binary_VGA_Controller
....................\..\.............................\hdl
....................\..\.............................\...\Binary_VGA_Control_IF_hw.tcl
....................\..\.............................\...\Binary_VGA_Control_IF_hw.tcl~
....................\..\.............................\...\Img_DATA.hex
....................\..\.............................\...\Img_RAM.v
....................\..\.............................\...\VGA_Controller.v
....................\..\.............................\...\VGA_NIOS_CTRL.v
....................\..\.............................\...\VGA_NIOS_CTRL.v.bak
....................\..\.............................\...\VGA_OSD_RAM.v
....................\..\.............................\...\VGA_Param.h
....................\..\.............................\software
....................\..\TERASIC_DM9000A
....................\..\...............\hdl
....................\..\...............\...\DM9000A_IF.v
....................\..\...............\...\DM9000A_IF_hw.tcl
....................\..\...............\...\DM9000A_IF_hw.tcl~
....................\..\...............\software
....................\..\...............\........\DM9000A.C
....................\..\...............\........\DM9000A.H
....................\..\TERASIC_ISP1362
....................\..\...............\hdl
....................\..\...............\...\ISP1362_IF.v
....................\..\...............\...\ISP1362_IF_hw.tcl
....................\..\...............\software
....................\..\TERASIC_SEG7
....................\..\............\hdl
....................\..\............\...\SEG7_IF.v
....................\..\............\...\SEG7_IF_hw.tcl
....................\..\............\software
....................\..\............\........\SEG7.c
....................\..\............\........\SEG7.h
....................\ISP1362.v
....................\SEG7.v
....................\VGA.v
....................\altpllpll.ppf
....................\altpllpll.qip
....................\altpllpll.v
....................\cpu.ocp
....................\cpu.sdc
....................\cpu.v
....................\cpu_bht_ram.mif
....................\cpu_dc_tag_ram.mif
....................\cpu_ic_tag_ram.mif
....................\cpu_jtag_debug_module_sys

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